dc.contributorFernandes, Marcelo Augusto Costa
dc.contributorhttp://lattes.cnpq.br/2532477079704883
dc.contributorhttp://lattes.cnpq.br/3475337353676349
dc.contributorGomes, Rafael Beserra
dc.contributorhttp://lattes.cnpq.br/5849107545126304
dc.contributorBrito Júnior, Agostinho de Medeiros
dc.contributorCarvalho, Marco Antonio Garcia de
dc.contributorhttp://lattes.cnpq.br/6366443994619479
dc.creatorBarros, Wysterlânya Kyury Pereira
dc.date.accessioned2022-03-09T16:40:48Z
dc.date.accessioned2022-10-06T13:42:04Z
dc.date.available2022-03-09T16:40:48Z
dc.date.available2022-10-06T13:42:04Z
dc.date.created2022-03-09T16:40:48Z
dc.date.issued2021-11-17
dc.identifierBARROS, Wysterlânya Kyury Pereira. Hardware implementation of the Otsu's method applied to realtime worm segmentation. 2021. 66f. Dissertação (Mestrado em Engenharia Elétrica e de Computação) - Centro de Tecnologia, Universidade Federal do Rio Grande do Norte, Natal, 2021.
dc.identifierhttps://repositorio.ufrn.br/handle/123456789/46475
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/3972197
dc.description.abstractBehavioral genomic studies employing the worm Caenorhabditis elegans have aided the discovery of new gene-behavioral associations and the screening of new drugs. Highresolution cameras record experiments with this worm, generating videos that computational solutions will later process for automated behavioral analysis. Because of the large volume of data to be processed, these analyses usually have to be performed offline. However, it is desired to develop a high-throughput implementation capable of operating in real-time, seeking to reduce the memory occupation by storing videos and allow the realization of new kinds of experiments. One way to speed up the algorithms employed is through the use of reconfigurable computing. Therefore, this work proposes the hardware development of the Otsu method for worm segmentation in real-time. The proposed implementation was developed in Field Programmable Gate Array (FPGA) using a fully parallel strategy with fixed-point representation. Architecture details are presented, as well as synthesis results related to the hardware area occupation, throughput, and dynamic power consumption. Results about validation of the implementation using images of the worms are also provided. The data show that the proposed architecture can achieve high speedups compared to similar work presented in the literature, besides allowing the segmentation of worms in real-time.
dc.publisherUniversidade Federal do Rio Grande do Norte
dc.publisherBrasil
dc.publisherUFRN
dc.publisherPROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E DE COMPUTAÇÃO
dc.rightsAcesso Aberto
dc.subjectFPGA
dc.subjectImage segmentation
dc.subjectOtsu's method
dc.subjectWorm tracking
dc.subjectC. elegans
dc.titleHardware implementation of the Otsu's method applied to realtime worm segmentation
dc.typemasterThesis


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