masterThesis
Proposta de implementação em hardware de rede neural profunda baseada em Stacked Sparse Autoencoder
Fecha
2019-01-17Registro en:
COUTINHO, Maria Gracielly Fernandes. Proposta de implementação em hardware de rede neural profunda baseada em Stacked Sparse Autoencoder. 2019. 70f. Dissertação (Mestrado em Engenharia Elétrica e de Computação) - Centro de Tecnologia, Universidade Federal do Rio Grande do Norte, Natal, 2019.
Autor
Coutinho, Maria Gracielly Fernandes
Resumen
The deep learning techniques have been gaining prominence in world research in the
past years. However, the deep learning algorithms have high computational cost, making
it hard to apply in several commercial applications. On the other hand, new alternatives
have been studying to accelerate complex algorithms, among these, those based on reconfigurable hardware has been showing very significant results. Therefore, the objective of
this work is the hardware implementation of a neural network for the use of algorithms
with deep learning. The hardware was developed on Field Programmable Gate Array
(FPGA) and supports Deep Neural Network (DNN) trained with the Stacked Sparse Autoencoder (SSAE) technique. In order to allow DNNs with many inputs and layers on the
FPGA, the systolic array technique was used in all developed hardware. The details of
the architecture designed on the FPGA were evidenced, as well as the occupation data on
hardware, the processing time and the power consumption to two different implementations. The results show that both implementations achieve high throughputs allowing the
use of Deep Learning techniques in massive data problems.