doctoralThesis
Proposta de arquitetura de alto desempenho para sistemas de tempo real
Fecha
2020-07-31Registro en:
SIQUEIRA, Hadley Magno da Costa. Proposta de arquitetura de alto desempenho para sistemas de tempo real. 2020. 104f. Tese (Doutorado em Ciência da Computação) - Centro de Ciências Exatas e da Terra, Universidade Federal do Rio Grande do Norte, Natal, 2020.
Autor
Siqueira, Hadley Magno da Costa
Resumen
Precision-Timed Machines (PRET) are architectures intended for use in real-time and
cyber physical cyber systems. The main feature of these architectures is that they provide
predictability and repeatability for real-time tasks, thus facilitating development, analysis
and testing of these systems. The state of the art, at the time of this writing, consists of
processors based on the PRET concept. These processors explores thread level parallelism
by interleaving threads at a fine-grained leve, i.e. at each clock cycle.This strategy provides
good performance when there is parallelism at the thread level, but induces a low performance in the absence of this parallelism. In addition, the switching of threads to each clock
cycle leads to high latency. This high latency can make it impossible performing tasks that
require low latency. The present work contributes for the state of the art in two ways: first
by presenting a proposal for a reconfigurable coarsed-grain reconfigurable array based on
the PRET concept. The proposed array is coupled to a PRET processor, providing support
for accelerating important parts of an application. The array was designed in such a way
that when coupled to the processor do not make the processor lose its original temporal
properties. The second contribution of this thesis is the proposal and implementation of
a multicore architecture. Each core is composed of a processor coupled to the proposed
array. Thus, this work seeks to present a high performance architecture facing embedded
real-time systems that have high demand for performance such as avionics, for example.
Results show that the proposed architecture it is capable of providing acceleration of more
than 10 times for some types of applications. In terms of area, synthesis results for FPGA
show that each core occupies less than half of a processor running out of order. In addition,
it has an area similar to other arrays used in low-power embedded systems