Generation of application specific fault tolerant irregular NoC topologies using tabu search

Abstract

Network on Chip (NoC) was proposed to enhance computer performance. Initially conceived topologies tended to have a regular structure, aiming flexibility - regular performance for different applications, and multiple paths between routers. Regular topologies lack in performance if compared to specific application generated topologies, often irregular. On the other hand, irregular topologies may lack flexibility. In the billion-transistor era, circuit components are more susceptible to faults, whether caused by radiation, electromagnetic interference or similar effects. Due to the cost of producing such circuits, it is desirable to increase their durability (lifespan), performance, and flexibility. Durability may be achieved by adding fault-tolerance to the circuit. Therefore, by adding redundant components - e.g. routers or links - to an irregular NoC, it may be possible to increase its durability and flexibility (multiple communication paths), though energy consumption may be impaired. This work proposes the generation of irregular topologies using Tabu Search. Thus generating intermediate topologies: flexible if compared to most irregular ones (some fault resistance), yet achieving application specific high performance if compared to regular NoCs.