masterThesis
Exploração de espaço de projeto para geração de redes em chip de topologias irregulares otimizadas: a rede UTNoC
Fecha
2016-12-08Registro en:
MESQUITA, Jonathan Wanderley de. Exploração de espaço de projeto para geração de redes em chip de topologias irregulares otimizadas: a rede UTNoC. 2016. 79f. Dissertação (Mestrado em Sistemas e Computação) - Centro de Ciências Exatas e da Terra, Universidade Federal do Rio Grande do Norte, Natal, 2016.
Autor
Mesquita, Jonathan Wanderley de
Resumen
During the design of multiprocessor architectures, the design space exploration step may
be aided by tools that assist and accelerate this process. The project of architectures
whose communications are based on Networks-on-Chip (NoCs), usually relies on regular
topologies, disregarding a possible irregularity in the communication pattern between the
interconnected elements. The present work proposes an irregular topology chip network,
capable of having good performance (close to the performance of a network connected
according to the application graph), through a communication process based on routing
tables. The work proposes also a high-level exploration tool using Genetic Algorithm, able
to find UTNoC networks with reduced number of connections, and assisting in the design
decisions of these networks. The obtained Results show that it’s possible to obtain UTNoC
networks with performances close to the performance of networks connected according to
the graphs of their applications, and with a reduction in the number of connections of up
to 54%, representing a significant reduction of area and energy consumption.