dc.contributor | Universidade Estadual Paulista (Unesp) | |
dc.date.accessioned | 2014-05-27T11:24:05Z | |
dc.date.accessioned | 2022-10-05T18:18:52Z | |
dc.date.available | 2014-05-27T11:24:05Z | |
dc.date.available | 2022-10-05T18:18:52Z | |
dc.date.created | 2014-05-27T11:24:05Z | |
dc.date.issued | 2009-12-01 | |
dc.identifier | IFAC Proceedings Volumes (IFAC-PapersOnline), v. 4, n. PART 1, p. 84-89, 2009. | |
dc.identifier | 1474-6670 | |
dc.identifier | http://hdl.handle.net/11449/71347 | |
dc.identifier | 10.3182/20091006-3-ES-4010.00017 | |
dc.identifier | 2-s2.0-79960933497 | |
dc.identifier | 2098623262892719 | |
dc.identifier | 0000-0003-1086-3312 | |
dc.identifier.uri | http://repositorioslatinoamericanos.uchile.cl/handle/2250/3920537 | |
dc.description.abstract | The constant increase in digital systems complexity definitely demands the automation of the corresponding synthesis process. This paper presents a computational environment designed to produce both software and hardware implementations of a system. The tool for code generation has been named ACG8051. As for the hardware synthesis there has been produced a larger environment consisting of four programs, namely: PIPE2TAB, AGPS, TABELA, and TAB2VHDL. ACG8051 and PIPE2TAB use place/transition net descriptions from PIPE as inputs. ACG8051 is aimed at generating assembly code for the 8051 micro-controller. PIPE2TAB produces a tabular version of a Mealy type finite state machine of the system, its output is fed into AGPS that is used for state allocation. The resulting digital system is then input to TABELA, which minimizes control functions and outputs of the digital system. Finally, the output generated by TABELA is fed to TAB2VHDL that produces a VHDL description of the system at the register transfer level. Thus, we present here a set of tools designed to take a high-level description of a digital system, represented by a place/transition net, and produces as output both an assembly code that can be immediately run on an 8051 micro-controller, and a VHDL description that can be used to directly implement the hardware parts either on an FPGA or as an ASIC. | |
dc.language | eng | |
dc.relation | IFAC Proceedings Volumes (IFAC-PapersOnline) | |
dc.rights | Acesso aberto | |
dc.source | Scopus | |
dc.subject | Design automation | |
dc.subject | Digital system synthesis | |
dc.subject | Finite state machine | |
dc.subject | Petri net | |
dc.subject | Assembly code | |
dc.subject | Code Generation | |
dc.subject | Computational environments | |
dc.subject | Control functions | |
dc.subject | Design automations | |
dc.subject | Digital system | |
dc.subject | Digital system design | |
dc.subject | Hardware implementations | |
dc.subject | Hardware synthesis | |
dc.subject | High level description | |
dc.subject | Place/transition Petri nets | |
dc.subject | Register transfer level | |
dc.subject | Synthesis process | |
dc.subject | VHDL description | |
dc.subject | Automation | |
dc.subject | Computer aided design | |
dc.subject | Computer hardware description languages | |
dc.subject | Finite automata | |
dc.subject | Hardware | |
dc.subject | Multiprocessing systems | |
dc.subject | Petri nets | |
dc.subject | Systems analysis | |
dc.title | Digital system design process automation using place/transition petri nets | |
dc.type | Trabalho apresentado em evento | |