An active leakage-injection scheme applied to low-voltage SRAMs

Abstract

An active leakage-injection scheme (ALIS) for low-voltage (LV) high-density (HD) SRAMs is presented. By means of a feedback loop comprising a servo-amplifier and a common-drain MOSFET, a current matching the respective bit-line leakage is injected onto the line during precharge and sensing, preventing the respective capacitances from erroneous discharges. The technique is able to handle leakages up to hundreds of μA at high operating temperatures. Since no additional timing is required, read-out operations are performed at no speed penalty. A simplified 256×1bit array was designed in accordance with a 0.35 CMOS process and 1.2V-supply. A range of PSPICE simulation attests the efficacy of ALIS. With an extra power consumption of 242 μW, a 200 μA-leakage @125°C, corresponding to 13.6 times the cell current, is compensated.