dc.contributorUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2014-05-20T15:23:26Z
dc.date.accessioned2022-10-05T16:22:08Z
dc.date.available2014-05-20T15:23:26Z
dc.date.available2022-10-05T16:22:08Z
dc.date.created2014-05-20T15:23:26Z
dc.date.issued2006-01-01
dc.identifier2006 IEEE International Symposium on Industrial Electronics, Vols 1-7. New York: IEEE, p. 1382-1387, 2006.
dc.identifierhttp://hdl.handle.net/11449/34230
dc.identifier10.1109/ISIE.2006.295674
dc.identifierWOS:000244382902064
dc.identifier6427185658143370
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/3906411
dc.description.abstractThis paper presents a multi-cell single-phase high power factor boost rectifier in interleave connection, operating in critical conduction mode, employing a soft-switching technique, and controlled by Field Programmable Gate Array (FPGA). The soft-switching technique is based on zero-current-switching (ZCS) cells, providing ZC (zero-current) turn-on and ZCZV (zero-current-zero-voltage) turn-off for the active switches, and ZV (zero-vohage) turn-on and ZC (zero-current) turn-off for the boost diodes. The disadvantages related to reverse recovery effects of boost diodes operated in continuous conduction mode (additional losses, and electromagnetic interference (EMI) problems) are minimized, due to the operation in critical conduction mode. In addition, due to the interleaving technique, the rectifier's features include the reduction in the input current ripple, the reduction in the output voltage ripple, the use of low stress devices, low volume for the EMI input filter, high input power factor (PF), and low total harmonic distortion (THD) in the input current, in compliance with the IEC61000-3-2 standards. The digital controller has been developed using a hardware description language (VHDL) and implemented using a XC2S200E-SpartanII-E/Xilinx FPGA device, performing a true critical conduction operation mode for all interleaved cells, and a closed-loop to provide the output voltage regulation, like as a preregulator rectifier. Experimental results are presented for a implemented prototype with two and with four interleaved cells, 400V nominal output voltage and 220V(rms) nominal input voltage, in order to verify the feasibility and performance of the proposed digital control through the use of a FPGA device.
dc.languageeng
dc.publisherIEEE
dc.relation2006 IEEE International Symposium on Industrial Electronics, Vols 1-7
dc.rightsAcesso aberto
dc.sourceWeb of Science
dc.titleA multi-cell variable frequency interleaved ZCS boost rectifier digitally controlled by FPGA
dc.typeTrabalho apresentado em evento


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