Monitoração dinâmica de asserções para depuração em silício

Abstract

The increasing demand for shorter time-to-market, combined with increased complexity and performance requirements put a tremendous pressure on post-silicon debug, which is usually the last step prior to chip release. In contrast to pre-silicon techniques, postsilicon debug have two main limitations, controllability and observability, which cause the failure analysis and identification to require significantly more efiort. Post-silicon debug is thus becoming a potential bottleneck in productivity and cost. Therefore it is emerging as one of the most important topics for research and the EDA industry. In this thesis, we present a novel technique to improve observability of circuits during post-silicon debug, where the choice of signals to be monitored is done accordingly to a failure detected. This technique requires an on-chip module to control signal selection, as well as an ofi-chip system to correctly integrate the debug architecture with the target circuit. The on-chip architecture employs a scan-chain to identify any assertion failure and a trace bufier to store the state of a limited set of internal signals. A design for debug module was then developed to integrate the identification of the assertion that has failed, acquired by the scan-chain, to a system that chooses which signals must be captured by the trace bufier in the next execution. One important aspect of the system is the correlation between the signals chosen to be captured and the assertion that has failed. Connection software was developed to do this selection in an early stage of development, before tape-out. This software implements the signal selection based on the cone of infiuence (COI) of the embedded assertions and it is also capable of gathering the assertions in clusters. Besides that, the developed software generates new register transfer level (RTL) code for the circuit under debug, including all the design for debug logic and the connections necessary to its proper functioning.The proposed architecture was tested using a MIPS32 based processor with 40 assertions. This case study is presented to illustrate the eficiency of our rchitecture. The entire debug fiow is reproduced, from design integration, then going through the bug detection and finally the extraction of relevant data to reproduce the error using a design verification tool. Furthermore, a separate study was done to analyze the method proposed for signal selection and it included the analysis of two more designs. The on-chip architecture had no impact over chip performance and the area overhead was minimum, thus it could be employed to post-silicon debug without any major impact. Additionally, the system was capable of extracting relevant data for the creation of lighthouses which were used to produce failing scenarios using a formal verification tool. On the other hand the signal selection based only on the cone of infiuence of the assertions was not sensitive enough to decrease the area of the chip to be analyzed. In more complex systems, the connection between the internal components of the designs analyzed were too high, resulting in cones of infiuence similar to the entire circuit and also between all properties. A second approach was then suggested considering the hierarchical position of signals in the cone of infiuence of each property. Although the signals of the COI sets are almost the same, the distance and the path to an assertion checker define the hierarchical configuration of its COI. The tests performed demonstrated that the second approach is a promising technique for selecting which areas of the chip should be observed according to an assertion failure. However, that approach still relies on the validation engineer knowledge of the system in addition to the development process, so it can be properly configured. In order to automate this process, more research should be done to refine the selection of which hierarchical instances should be considered for the signal selection.