dc.contributor | Diogenes Cecilio da Silva Junior | |
dc.creator | Rodrigo Durães de Vasconcellos | |
dc.date.accessioned | 2019-08-13T13:46:57Z | |
dc.date.accessioned | 2022-10-03T23:08:13Z | |
dc.date.available | 2019-08-13T13:46:57Z | |
dc.date.available | 2022-10-03T23:08:13Z | |
dc.date.created | 2019-08-13T13:46:57Z | |
dc.date.issued | 2011-12-07 | |
dc.identifier | http://hdl.handle.net/1843/BUOS-8UJJ7V | |
dc.identifier.uri | http://repositorioslatinoamericanos.uchile.cl/handle/2250/3817357 | |
dc.description.abstract | This work presents the project of a 12-bit successive approximation analog-to-digital converter (SAR ADC). The mixed-signal development stages use a specific methodology that starts with the design of high abstraction level models and ends with the design of an integrated circuit (IC). The stages are fulfilled with the help of tools such as Stateflow,Simscape, SystemC/SystemC-AMS and Cadence Design Framework II. The converter development comes from the increasing demand for mixed-signal subsystems integrated into a SoC (System on Chip). | |
dc.publisher | Universidade Federal de Minas Gerais | |
dc.publisher | UFMG | |
dc.rights | Acesso Aberto | |
dc.subject | Aproximações Sucessivas | |
dc.subject | SystemCAMS | |
dc.subject | Stateflow | |
dc.subject | Conversor Analógico/Digital | |
dc.subject | Simscape | |
dc.subject | Circuito Integrado | |
dc.subject | SystemC | |
dc.title | Projeto de um conversor analógico/digital por aproximações sucessivas de 12 bits | |
dc.type | Dissertação de Mestrado | |