Geração de especificações executáveis para o projeto de módulos para sistemas em "Chips"

Abstract

The increasing demand for electronic components is driving the integrated circuit market to an unexpected growth. In the about two to four years it will be possible to find circuits composed of a billion transistors. This capacity of integration is the responsible for the emergence of a new concept, System-on-a-chip (SoC), in which a complete computational system is embedded into an single integrated circuit. The high complexity of the process of integration and the interconnection of the modules,named Intellectual Property (IP), that composes a SoC, are demanding that the designers of these modules to invest more and more time in the search of new design methodologies. The time spent in the development process of SoC design is also one of the main factors that contribute to the need of new design methodologies. This work presents the proposal of a new SoC design methodology that will make possible a onsiderable reduction in the time of development and test of the SoC design process through the generation of an executable specification that will be used as a reference model. The methodology utilizes UML diagrams for the system description. For the description of the modules in their levels of abstraction, the methodology makes use of the hardware description language SystemC environment.