A Hardware Accelerator for the Inference of a Convolutional Neural network

Acelerador en hardware para la inferencia de una red neuronal convolucional

dc.creatorGonzález , Edwin
dc.creatorVillamizar Luna , Walter D.
dc.creatorFajardo Ariza, Carlos Augusto
dc.date2019-11-12
dc.identifierhttps://revistas.unimilitar.edu.co/index.php/rcin/article/view/4194
dc.identifier10.18359/rcin.4194
dc.descriptionConvolutional Neural Networks (CNNs) are becoming increasingly popular in deep learning applications, e.g. image classification, speech recognition, medicine, to name a few. However, the CNN inference is computationally intensive and demanding a large among of memory resources. In this work is proposed a CNN inference hardware accelerator, which was implemented in a co-processing scheme. The aim is to reduce the hardware resources and achieve the better possible throughput. The design was implemented in the Digilent Arty Z7-20 development board, which is based on System on Chip (SoC) Zynq-7000 of Xilinx. Our implementation achieved a  of accuracy for the MNIST database using only 12-bits fixed-point format. The results show that the co-processing scheme operating at a conservative speed of 100 MHz can identify around 441 images per second, which is about 17% times faster than a 650 MHz - software implementation. It is difficult to compare our results against other implementations based on Field-Programmable Gate Array (FPGA), because the others implementations are not exactly like ours. However, some comparisons, regarding the logical resources used and accuracy, suggest that our work could be better than previous works.
dc.descriptionLas redes neuronales convolucionales cada vez son más populares en aplicaciones de aprendizaje profundo, como por ejemplo en clasificación de imágenes, reconocimiento de voz, medicina, entre otras. Sin embargo, estas redes son computacionalmente costosas y requieren altos recursos de memoria. En este trabajo se propone un acelerador en hardware para el proceso de inferencia de la red Lenet-5, un esquema de co-procesamiento hardware/software. El objetivo de la implementación es reducir el uso de recursos de hardware y obtener el mejor rendimiento computacional posible durante el proceso de inferencia. El diseño fue implementado en la tarjeta de desarrollo Digilent Arty Z7-20, la cual está basada en el System on Chip (SoC) Zynq-7000 de Xilinx. Nuestra implementación logró una precisión del 97.59% para la base de datos MNIST utilizando tan solo 12 bits en el formato de punto fijo. Los resultados muestran que el esquema de co-procesamiento, el cual opera a una velocidad de 100 MHz, puede identificar aproximadamente 441 imágenes por segundo, que equivale aproximadamente a un 17% más rápido que una implementación de software a 650 MHz. Es difícil comparar nuestra implementación con otras implementaciones similares, porque las implementaciones encontradas en la literatura no son exactamente como la que realizó en este trabajo. Sin embargo, algunas comparaciones, en relación con el uso de recursos lógicos y la precisión, sugieren que nuestro trabajo supera a trabajos previos.
dc.formatapplication/pdf
dc.formattext/xml
dc.languageeng
dc.publisherUniversidad Militar Nueva Granada
dc.relationhttps://revistas.unimilitar.edu.co/index.php/rcin/article/view/4194/4084
dc.relationhttps://revistas.unimilitar.edu.co/index.php/rcin/article/view/4194/4255
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dc.rightsDerechos de autor 2019 Ciencia e Ingeniería Neogranadina
dc.sourceCiencia e Ingenieria Neogranadina; Vol. 30 No. 1 (2020); 107-116
dc.sourceCiencia e Ingeniería Neogranadina; Vol. 30 Núm. 1 (2020); 107-116
dc.sourceCiencia e Ingeniería Neogranadina; v. 30 n. 1 (2020); 107-116
dc.source1909-7735
dc.source0124-8170
dc.subjectCNN
dc.subjectFPGA
dc.subjectHardware accelerator
dc.subjectMNIST
dc.subjectZynq
dc.subjectCNN, FPGA, Hardware Accelerator, MNIST, Zynq.
dc.titleA Hardware Accelerator for the Inference of a Convolutional Neural network
dc.titleAcelerador en hardware para la inferencia de una red neuronal convolucional
dc.typeinfo:eu-repo/semantics/article
dc.typeinfo:eu-repo/semantics/publishedVersion
dc.typeText
dc.typeTexto


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