Towards a field configurable non-homogeneous multiprocessors architecture

dc.creatorJaquenod, Guillermo A.
dc.creatorVillagarcía Wanza, Horacio Alfredo
dc.creatorDe Giusti, Marisa Raquel
dc.date2001
dc.date.accessioned2019-05-28T11:04:24Z
dc.date.available2019-05-28T11:04:24Z
dc.identifierhttp://digital.cic.gba.gob.ar/handle/11746/1546
dc.identifierDocumento Completo
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/2858396
dc.descriptionStandard microprocessors are generally designed to deal efficiently with different types of tasks; their general purpose architecture can lead to misuse of resources, creating a large gap between the computational efficiency of microprocessors and custom silicon. The ever increasing complexity of Field Programmable Logic devices is driving the industry to look for innovative System on a Chip solutions; using programmable logic, the whole design can be tuned to the application requirements. In this paper, under the acronym MPOC (Multiprocessors On a Chip) we propose some applicable ideas on multiprocessing embedded configurable architectures, targeting System on a Programmable Chip (SOPC) cost-effective designs. Using heterogeneous medium or low performance soft-core processors instead of a single high performance processor, and some standardized communication schemes to link these multiple processors, the “best” core can be chosen for each subtask using a computational efficiency criteria, and therefore improving silicon usage. System-level design is also considered: models of tasks and links, parameterized soft-core processors, and the use of a standard HDL for system description can lead to automatic generation of the final design.
dc.formatapplication/pdf
dc.format6 p.
dc.languageInglés
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightsAttribution 4.0 International (BY 4.0)
dc.subjectCiencias de la Computación
dc.titleTowards a field configurable non-homogeneous multiprocessors architecture


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