dc.contributor | Pedrino, Emerson Carlos | |
dc.contributor | http://lattes.cnpq.br/6481363465527189 | |
dc.contributor | http://lattes.cnpq.br/2889169146811970 | |
dc.creator | Almeida, Manoel Aranda de | |
dc.date.accessioned | 2016-10-20T18:28:13Z | |
dc.date.available | 2016-10-20T18:28:13Z | |
dc.date.created | 2016-10-20T18:28:13Z | |
dc.date.issued | 2016-03-04 | |
dc.identifier | ALMEIDA, Manoel Aranda de. Sistema embarcado reconfigurável de forma estática por programação genética utilizando hardware evolucionário híbrido. 2016. Dissertação (Mestrado em Ciência da Computação) – Universidade Federal de São Carlos, São Carlos, 2016. Disponível em: https://repositorio.ufscar.br/handle/ufscar/8000. | |
dc.identifier | https://repositorio.ufscar.br/handle/ufscar/8000 | |
dc.description.abstract | The use of technology based on Field Programmable Gate Arrays (FPGAs), a
reconfigurable technology, has become a frequent object of study. This technique is
feasible and a promising application in the development of embedded systems, however,
the difficulty in finding a flexible and efficient way to perform such an application is their
bigger problem. In this work, a virtual and reconfigurable architecture (AVR) in FPGA for
hardware applications is presented using a Genetic Programming Software on the
development of an optimal reconfiguration for this AVR, in order to build a hardware
capable of performing a given task in an embedded system. This proposal is a simple,
flexible and efficient way to achieve appropriate applications in embedded systems, when
compared to other reconfigurable hardware techniques. The representation of phenotype
of the proposed evolutionary system is based on a bi-dimensional network function
elements (EF). The GPLAB tool for MATLAB is used in Genetic Programming, and the
solution found by this procedure is converted into a memory mapping to represent the best
solution, where it is used to reconfigure the hardware. In the tests, GPLAB found results
for logic circuits in a few generations, and for image filters containing efficient solutions,
where there was little hardware occupation, especially memory, in the cases this has been
presented, with a reduced chromosome size, shows a proposal efficiency. | |
dc.language | por | |
dc.publisher | Universidade Federal de São Carlos | |
dc.publisher | UFSCar | |
dc.publisher | Programa de Pós-Graduação em Ciência da Computação - PPGCC | |
dc.publisher | Câmpus São Carlos | |
dc.rights | Acesso aberto | |
dc.subject | Arquitetura virtual reconfigurável | |
dc.subject | FPGA | |
dc.subject | Hardware evolucionário | |
dc.subject | GPLAB | |
dc.subject | Programação genética | |
dc.subject | Virtual Reconfigurable Architecture | |
dc.subject | Field Programmable Gate Arrays | |
dc.subject | Evolvable Hardware | |
dc.subject | Genetic programming | |
dc.subject | Cartesian genetic programming | |
dc.subject | Embedded systems | |
dc.subject | Programming embedded systems | |
dc.subject | Digital Image Processing | |
dc.title | Sistema embarcado reconfigurável de forma estática por programação genética utilizando hardware evolucionário híbrido | |
dc.type | Tesis | |