n-Channel bulk and DTMOS FinFETs: Investigation of GIDL and gate leakage currents

dc.contributorUniversidade Estadual Paulista (Unesp)
dc.contributorUniversidade de São Paulo (USP)
dc.contributorImec
dc.contributorKU Leuven
dc.date.accessioned2018-12-11T17:30:50Z
dc.date.available2018-12-11T17:30:50Z
dc.date.created2018-12-11T17:30:50Z
dc.date.issued2016-11-02
dc.identifierSBMicro 2016 - 31st Symposium on Microelectronics Technology and Devices: Chip on the Mountains, co-located 29th SBCCI - Circuits and Systems Design, 6th WCAS - IC Design Cases, 1st INSCIT - Electronic Instrumentation and 16th SForum - Undergraduate-Student Forum.
dc.identifierhttp://hdl.handle.net/11449/178539
dc.identifier10.1109/SBMicro.2016.7731350
dc.identifier2-s2.0-85007329860
dc.description.abstractIn this work GIDL (Gate Induced Drain Leakage) and Gate Leakage Currents (Ig) have been experimentally investigated for different dimensions of Bulk FinFETs with and without Dynamic Threshold MOS configuration (DTMOS) in linear and saturation regions. The results indicate that Bulk FinFETs present lower gate leakage currents than DTMOS FinFETs. In addition, an opposite IG behavior of those devices was observed when the channel lengths change. On the other hand, for long channels FinFETs the GIDL effect is lower in devices with DTMOS configuration because the benefit of DTMOS operation becomes higher.
dc.languageeng
dc.relationSBMicro 2016 - 31st Symposium on Microelectronics Technology and Devices: Chip on the Mountains, co-located 29th SBCCI - Circuits and Systems Design, 6th WCAS - IC Design Cases, 1st INSCIT - Electronic Instrumentation and 16th SForum - Undergraduate-Student Forum
dc.rightsAcesso aberto
dc.sourceScopus
dc.subjectBulk
dc.subjectDTMOS
dc.subjectGIDL
dc.subjectIG
dc.subjectleakage current
dc.titlen-Channel bulk and DTMOS FinFETs: Investigation of GIDL and gate leakage currents
dc.typeActas de congresos


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