dc.contributor | Universidade de São Paulo (USP) | |
dc.contributor | Universidade Estadual Paulista (Unesp) | |
dc.contributor | imec | |
dc.contributor | Ghent University | |
dc.contributor | KU Leuven | |
dc.date.accessioned | 2018-12-11T16:42:27Z | |
dc.date.available | 2018-12-11T16:42:27Z | |
dc.date.created | 2018-12-11T16:42:27Z | |
dc.date.issued | 2016-09-01 | |
dc.identifier | Solid-State Electronics, v. 123, p. 124-129. | |
dc.identifier | 0038-1101 | |
dc.identifier | http://hdl.handle.net/11449/168671 | |
dc.identifier | 10.1016/j.sse.2016.05.004 | |
dc.identifier | 2-s2.0-84969508640 | |
dc.identifier | 2-s2.0-84969508640.pdf | |
dc.identifier | 0496909595465696 | |
dc.identifier | 0000-0002-0886-7798 | |
dc.description.abstract | This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25 °C to 150 °C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs. | |
dc.language | eng | |
dc.relation | Solid-State Electronics | |
dc.relation | 0,492 | |
dc.rights | Acesso aberto | |
dc.source | Scopus | |
dc.subject | Analog parameters | |
dc.subject | Bulk pFinFET | |
dc.subject | High temperature | |
dc.subject | SOI pFinFET | |
dc.title | Comparative analysis of the intrinsic voltage gain and unit gain frequency between SOI and bulk FinFETs up to high temperatures | |
dc.type | Artículos de revistas | |