dc.contributor | Universidade de São Paulo (USP) | |
dc.contributor | Universidade Estadual Paulista (Unesp) | |
dc.contributor | Imec | |
dc.contributor | Univ Ghent | |
dc.contributor | Katholieke Univ Leuven | |
dc.date.accessioned | 2018-11-26T15:47:29Z | |
dc.date.available | 2018-11-26T15:47:29Z | |
dc.date.created | 2018-11-26T15:47:29Z | |
dc.date.issued | 2017-01-01 | |
dc.identifier | 2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017). New York: Ieee, p. 180-183, 2017. | |
dc.identifier | 2330-5738 | |
dc.identifier | http://hdl.handle.net/11449/160099 | |
dc.identifier | WOS:000425210900048 | |
dc.identifier | 0496909595465696 | |
dc.identifier | 0000-0002-0886-7798 | |
dc.description.abstract | The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to the strained one, since the latter presents a higher source/drain leakage current. Considering a figure of merit for analog applications, i.e., intrinsic voltage gain AV, no relevant difference between the relaxed and strained channel performances has been shown for short devices while the relaxed ones present a higher Av for longer devices. | |
dc.language | eng | |
dc.publisher | Ieee | |
dc.relation | 2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017) | |
dc.rights | Acesso aberto | |
dc.source | Web of Science | |
dc.subject | FinFET | |
dc.subject | germanium | |
dc.subject | p-type | |
dc.subject | strained | |
dc.subject | relaxed | |
dc.title | Experimental comparison between relaxed and strained Ge pFinFETs | |
dc.type | Actas de congresos | |