dc.contributorUniversidade de São Paulo (USP)
dc.contributorUniversidade Estadual Paulista (Unesp)
dc.contributorImec
dc.contributorUniv Ghent
dc.contributorKatholieke Univ Leuven
dc.date.accessioned2018-11-26T15:47:29Z
dc.date.available2018-11-26T15:47:29Z
dc.date.created2018-11-26T15:47:29Z
dc.date.issued2017-01-01
dc.identifier2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017). New York: Ieee, p. 180-183, 2017.
dc.identifier2330-5738
dc.identifierhttp://hdl.handle.net/11449/160099
dc.identifierWOS:000425210900048
dc.identifier0496909595465696
dc.identifier0000-0002-0886-7798
dc.description.abstractThe experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to the strained one, since the latter presents a higher source/drain leakage current. Considering a figure of merit for analog applications, i.e., intrinsic voltage gain AV, no relevant difference between the relaxed and strained channel performances has been shown for short devices while the relaxed ones present a higher Av for longer devices.
dc.languageeng
dc.publisherIeee
dc.relation2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017)
dc.rightsAcesso aberto
dc.sourceWeb of Science
dc.subjectFinFET
dc.subjectgermanium
dc.subjectp-type
dc.subjectstrained
dc.subjectrelaxed
dc.titleExperimental comparison between relaxed and strained Ge pFinFETs
dc.typeActas de congresos


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