Set-reset flip-flop circuit with a simple output logic

dc.creatorERIC CAMPOS CANTON
dc.creatorHARET CODRATIAN ROSU
dc.date2012
dc.date.accessioned2018-11-19T13:51:01Z
dc.date.available2018-11-19T13:51:01Z
dc.identifierhttp://ipicyt.repositorioinstitucional.mx/jspui/handle/1010/941
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/2252069
dc.description"The equation of the plane (EOP) in analytic geometry is used to build a logic dynamic architecture, i.e., a combination of set-reset flip-flop (SR-FF) and basic logic gates. This is achieved by using two of the variables in the EOP as the input signals of the SR-FF and the remaining variable as the output signal. This theoretical proposal for mixing the SR-FF and the basic logic gates is confirmed experimentally by means of a simple electronic implementation."
dc.formatapplication/pdf
dc.languageeng
dc.publisherSpringer Link
dc.relationinfo:eu-repo/semantics/altIdentifier/DOI/https://doi.org/10.1007/s00034-011-9343-4
dc.relationcitation:Campos-Cantón, I., Campos-Cantón, E., Rosu, H.C. et al. Circuits Syst Signal Process (2012) 31: 753.
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightshttp://creativecommons.org/licenses/by-nc-nd/4.0
dc.subjectinfo:eu-repo/classification/Autor/Set-reset flip-flop
dc.subjectinfo:eu-repo/classification/Autor/Equation of the plane
dc.subjectinfo:eu-repo/classification/Autor/Basic logic gates
dc.subjectinfo:eu-repo/classification/Autor/Bistable multivibrator
dc.subjectinfo:eu-repo/classification/cti/1
dc.titleSet-reset flip-flop circuit with a simple output logic
dc.typeArtículos de revistas
dc.typeinfo:eu-repo/semantics/submittedVersion
dc.audiencegeneralPublic


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