| dc.creator | SIMAO, Adenilso | |
| dc.creator | PETRENKO, Alexandre | |
| dc.date.accessioned | 2012-10-20T03:36:11Z | |
| dc.date.accessioned | 2018-07-04T15:38:53Z | |
| dc.date.available | 2012-10-20T03:36:11Z | |
| dc.date.available | 2018-07-04T15:38:53Z | |
| dc.date.created | 2012-10-20T03:36:11Z | |
| dc.date.issued | 2010 | |
| dc.identifier | IEEE TRANSACTIONS ON COMPUTERS, v.59, n.8, p.1023-1032, 2010 | |
| dc.identifier | 0018-9340 | |
| dc.identifier | http://producao.usp.br/handle/BDPI/28989 | |
| dc.identifier | 10.1109/TC.2010.17 | |
| dc.identifier | http://dx.doi.org/10.1109/TC.2010.17 | |
| dc.identifier.uri | http://repositorioslatinoamericanos.uchile.cl/handle/2250/1625631 | |
| dc.description.abstract | In testing from a Finite State Machine (FSM), the generation of test suites which guarantee full fault detection, known as complete test suites, has been a long-standing research topic. In this paper, we present conditions that are sufficient for a test suite to be complete. We demonstrate that the existing conditions are special cases of the proposed ones. An algorithm that checks whether a given test suite is complete is given. The experimental results show that the algorithm can be used for relatively large FSMs and test suites. | |
| dc.language | eng | |
| dc.publisher | IEEE COMPUTER SOC | |
| dc.relation | Ieee Transactions on Computers | |
| dc.rights | Copyright IEEE COMPUTER SOC | |
| dc.rights | restrictedAccess | |
| dc.subject | Finite State Machine | |
| dc.subject | test analysis | |
| dc.subject | fault coverage | |
| dc.subject | test completeness conditions | |
| dc.subject | test generation | |
| dc.title | Checking Completeness of Tests for Finite State Machines | |
| dc.type | Artículos de revistas | |
