dc.creatorBUENO, A. M.
dc.creatorRIGON, A. G.
dc.creatorFERREIRA, A. A.
dc.creatorPIQUEIRA, Jose R. C.
dc.date.accessioned2012-10-19T01:46:45Z
dc.date.accessioned2018-07-04T14:51:47Z
dc.date.available2012-10-19T01:46:45Z
dc.date.available2018-07-04T14:51:47Z
dc.date.created2012-10-19T01:46:45Z
dc.date.issued2010
dc.identifierCOMMUNICATIONS IN NONLINEAR SCIENCE AND NUMERICAL SIMULATION, v.15, n.9, p.2565-2574, 2010
dc.identifier1007-5704
dc.identifierhttp://producao.usp.br/handle/BDPI/18685
dc.identifier10.1016/j.cnsns.2009.09.039
dc.identifierhttp://dx.doi.org/10.1016/j.cnsns.2009.09.039
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1615477
dc.description.abstractClock signal distribution in telecommunication commercial systems usually adopts a master-slave architecture, with a precise time basis generator as a master and phase-locked loops (PLLs) as slaves. In the majority of the networks, second-order PLLs are adopted due to their simplicity and stability. Nevertheless, in some applications better transient responses are necessary and, consequently, greater order PLLs need to be used, in spite of the possibility of bifurcations and chaotic attractors. Here a master-slave network with third-order PLLs is analyzed and conditions for the stability of the synchronous state are derived, providing design constraints for the node parameters, in order to guarantee stability and reachability of the synchronous state for the whole network. Numerical simulations are carried out in order to confirm the analytical results. (C) 2009 Elsevier B.V. All rights reserved.
dc.languageeng
dc.publisherELSEVIER SCIENCE BV
dc.relationCommunications in Nonlinear Science and Numerical Simulation
dc.rightsCopyright ELSEVIER SCIENCE BV
dc.rightsclosedAccess
dc.subjectPhase-locked loop
dc.subjectSecond-order filter
dc.subjectSynchronization
dc.subjectStability
dc.titleDesign constraints for third-order PLL nodes in master-slave clock distribution networks
dc.typeArtículos de revistas


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