dc.creatorBUENO, Atila Madureira
dc.creatorFERREIRA, Andre Alves
dc.creatorPIQUEIRA, Jose Roberto Castilho
dc.date.accessioned2012-10-19T01:46:42Z
dc.date.accessioned2018-07-04T14:51:45Z
dc.date.available2012-10-19T01:46:42Z
dc.date.available2018-07-04T14:51:45Z
dc.date.created2012-10-19T01:46:42Z
dc.date.issued2010
dc.identifierIEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.57, n.12, p.3104-3111, 2010
dc.identifier1549-8328
dc.identifierhttp://producao.usp.br/handle/BDPI/18677
dc.identifier10.1109/TCSI.2010.2052514
dc.identifierhttp://dx.doi.org/10.1109/TCSI.2010.2052514
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1615469
dc.description.abstractOne-way master-slave (OWMS) chain networks are widely used in clock distribution systems due to their reliability and low cost. As the network nodes are phase-locked loops (PLLs), double-frequency jitter (DFJ) caused by their phase detectors appears as an impairment to the performance of the clock recovering process found in communication systems and instrumentation applications. A nonlinear model for OWMS chain networks with P + 1 order PLLs as slave nodes is presented, considering the DFJ. Since higher order filters are more effective in filtering DFJ, the synchronous state stability conditions for an OWMS chain network with third-order nodes are derived, relating the loop gain and the filter coefficients. By using these conditions, design examples are discussed.
dc.languageeng
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.relationIeee Transactions on Circuits and Systems I-regular Papers
dc.rightsCopyright IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
dc.rightsrestrictedAccess
dc.subjectClock distribution
dc.subjectdouble-frequency jitter
dc.subjectlow-pass filter
dc.subjectphase-locked loop
dc.subjectsynchronization
dc.titleModeling and Filtering Double-Frequency Jitter in One-Way Master-Slave Chain Networks
dc.typeArtículos de revistas


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