Architecting A Computer With A Full Optical Ram

dc.creatorGonzalez
dc.creatorJorge; Orosa
dc.creatorLois; Azevedo
dc.creatorRodolfo
dc.date2016
dc.date2017-11-13T13:50:59Z
dc.date2017-11-13T13:50:59Z
dc.date.accessioned2018-03-29T06:07:29Z
dc.date.available2018-03-29T06:07:29Z
dc.identifier978-1-5090-6113-6
dc.identifier23rd Ieee International Conference On Electronics Circuits And Systems (icecs 2016). Ieee, p. 716 - 719, 2016.
dc.identifierWOS:000399230200185
dc.identifier10.1109/ICECS.2016.7841302
dc.identifierhttp://ieeexplore.ieee.org/document/7841302/
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/329318
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1366343
dc.descriptionOn-chip photonics has gained attention in research for high-speed processor communication networks, and recent. developments in optical fabrication techniques and data buffering has offered new opportunities for processor systems. In this work, we evaluate a processor with a full optical main memory system. We design it using recent optical devices that leverages the high-bandwidth optical capabilities to obtain low memory access latency, similar to those in state of the art L2 caches. This characteristic enables the possibility of eliminating the second level of caches, saving processor area. Experimental results show the average speedup is x 1.34 with SPEC2006 and x1.80 with irregular applications.
dc.description716
dc.description719
dc.description23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS)
dc.descriptionDEC 11-14, 2016
dc.descriptionMONACO
dc.description
dc.languageEnglish
dc.publisherIEEE
dc.publisherNew York
dc.relation23rd IEEE international Conference on Electronics Circuits and Systems (ICECS 2016)
dc.rightsfechado
dc.sourceWOS
dc.titleArchitecting A Computer With A Full Optical Ram
dc.typeActas de congresos


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