dc.creatorNunes
dc.creatorR. O.; de Orio
dc.creatorR. L.
dc.date2016
dc.date2017-11-13T13:50:50Z
dc.date2017-11-13T13:50:50Z
dc.date.accessioned2018-03-29T06:07:23Z
dc.date.available2018-03-29T06:07:23Z
dc.identifier978-1-5090-2788-0
dc.identifier2016 31st Symposium On Microelectronics Technology And Devices (sbmicro). Ieee, p. , 2016.
dc.identifierWOS:000392469000014
dc.identifier10.1109/SBMicro.2016.7731325
dc.identifierhttp://ieeexplore.ieee.org/document/7731325/
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/329290
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1366315
dc.descriptionCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
dc.descriptionElectromigration damage in interconnects is a well-known bottleneck of integrated circuits, as it is responsible for performance degradation, affecting parameters like delay, power and frequency. To guarantee a better performance for longer time, the chip designer needs to identify critical wires in the circuit layout and to alter it using techniques that retard the electromigration impact on the circuit. In this work, it is proposed a methodology to identify the critical lines due to the electromigration effect. This methodology is applied to evaluate the performance degradation of a ring oscillator.
dc.descriptionBrazilian agency CAPES
dc.descriptionCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
dc.description31st Symposium on Microelectronics Technology and Devices (SBMicro)
dc.descriptionAUG 29-SEP 03, 2016
dc.descriptionBelo Horizonte, BRAZIL
dc.description
dc.languageEnglish
dc.publisherIEEE
dc.publisherNew York
dc.relation2016 31st Symposium on Microelectronics Technology and Devices (SBMICRO)
dc.rightsfechado
dc.sourceWOS
dc.subjectElectromigration
dc.subjectCrtical Interconnect
dc.subjectChip Reliability
dc.titleA Methodology To Identify Critical Interconnects Affected By Electromigration
dc.typeActas de congresos


Este ítem pertenece a la siguiente institución