On The Dark Silicon Automatic Evaluation On Multicore Processors

dc.creatorSantos
dc.creatorTony; Silva
dc.creatorAna; Duenha
dc.creatorLiana; Santos
dc.creatorRicardo; Moreno
dc.creatorEdward; Azevedo
dc.creatorRodolfo
dc.date2016
dc.date2017-11-13T13:22:40Z
dc.date2017-11-13T13:22:40Z
dc.date.accessioned2018-03-29T05:55:26Z
dc.date.available2018-03-29T05:55:26Z
dc.identifier978-1-5090-6108-2
dc.identifierProceedings Of 28th Ieee International Symposium On Computer Architecture And High Performance Computing. Ieee, p. 166 - 173, 2016.
dc.identifier1550-6533
dc.identifierWOS:000391392400021
dc.identifier10.1109/SBAC-PAD.2016.29
dc.identifierhttp://ieeexplore.ieee.org/document/7789337/
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/327942
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1364967
dc.descriptionThe advent of Dark Silicon as result of the limit on Dennard scaling forced modern processor designs to reduce the chip area that can work on maximum clock frequency. This effect reduced the free gains from Moore's law. This work introduces a less conservative dark silicon estimate based on chip components power density and technological process, so that designers could explore architectural resources to mitigate it. We implemented our dark silicon estimation tool on top of MultiExplorer and evaluated on a set of Intel Pentium and AMD K8/10 multicore processors built on transistor technologies from 90nm down to 32nm. Our contributions are twofold: (1) Our experiments have shown dark silicon estimates up to 8.26% of the chip area compared to a baseline 90nm real processor; we also evaluated clock frequency behavior based on Dennard scaling and obtained up to 15.65% dark silicon on chip area. (2) We designed and showed that a dark silicon aware Design Space Exploration (DSE) strategy can minimize chip dark area while increasing performance at design time. Our results on DSE found dark silicon free multicore platforms while providing 3.6 speedup.
dc.description166
dc.description173
dc.description28th IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)
dc.descriptionOCT 26-28, 2016
dc.descriptionLos Angeles, CA
dc.description
dc.languageEnglish
dc.publisherIEEE
dc.publisherNew York
dc.relationProceedings of 28th IEEE International Symposium on Computer Architecture and High Performance Computing
dc.rightsfechado
dc.sourceWOS
dc.subjectDark Silicon
dc.subjectMultiexplorer
dc.subjectEda
dc.subjectEstimates
dc.titleOn The Dark Silicon Automatic Evaluation On Multicore Processors
dc.typeActas de congresos


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