| dc.creator | Dias, JAS | |
| dc.creator | do Amaral, WA | |
| dc.creator | de Moraes, WB | |
| dc.date | 2009 | |
| dc.date | DEC | |
| dc.date | 2014-11-19T10:39:10Z | |
| dc.date | 2015-11-26T18:02:23Z | |
| dc.date | 2014-11-19T10:39:10Z | |
| dc.date | 2015-11-26T18:02:23Z | |
| dc.date.accessioned | 2018-03-29T00:44:04Z | |
| dc.date.available | 2018-03-29T00:44:04Z | |
| dc.identifier | Microelectronics Journal. Elsevier Sci Ltd, v. 40, n. 12, n. 1772, n. 1778, 2009. | |
| dc.identifier | 0026-2692 | |
| dc.identifier | WOS:000273105300013 | |
| dc.identifier | 10.1016/j.mejo.2009.10.001 | |
| dc.identifier | http://www.repositorio.unicamp.br/jspui/handle/REPOSIP/53095 | |
| dc.identifier | http://www.repositorio.unicamp.br/handle/REPOSIP/53095 | |
| dc.identifier | http://repositorio.unicamp.br/jspui/handle/REPOSIP/53095 | |
| dc.identifier.uri | http://repositorioslatinoamericanos.uchile.cl/handle/2250/1292221 | |
| dc.description | A novel technique for the design of very low temperature coefficient (TC) voltage references in a CMOS standard process is presented. The proposed circuit uses an all CMOS technique to generate a low TC voltage reference over a wide temperature range. A self-biased V-th (threshold voltage) generator circuit creates a voltage equal to the V-th of a CMOS transistor; this voltage is used to generate a current proportional to V-th(2), that, when forced into another transistor, creates a voltage which presents a negative non-linear temperature coefficient. A voltage with a positive TC, which can be controlled by the aspect ratio of a pair of transistors, is generated by a current mirror asymmetrically degenerated with a high-poly resistor. A curvature correction, provided by a current proportional to V-th(2), is used to modify the thermal behaviour of this positive TC voltage. By adding the positive and negative TCs voltages, a very stable reference voltage can be obtained. The circuit was designed to be implemented in a standard CMOS process (AMS 0.35 mu m), and simulated results indicate that a variation of only 2.5 ppm/degrees C is expected over the temperature range of 0-90 degrees C. (C) 2009 Elsevier Ltd. All rights reserved. | |
| dc.description | 40 | |
| dc.description | 12 | |
| dc.description | 1772 | |
| dc.description | 1778 | |
| dc.language | en | |
| dc.publisher | Elsevier Sci Ltd | |
| dc.publisher | Oxford | |
| dc.publisher | Inglaterra | |
| dc.relation | Microelectronics Journal | |
| dc.relation | Microelectron. J. | |
| dc.rights | fechado | |
| dc.rights | http://www.elsevier.com/about/open-access/open-access-policies/article-posting-policy | |
| dc.source | Web of Science | |
| dc.subject | CMOS voltage reference | |
| dc.subject | Temperature coefficient | |
| dc.subject | Analogue circuits | |
| dc.subject | Curvature compensation | |
| dc.title | A curvature-compensated CMOS voltage reference using V-th(2) characteristics | |
| dc.type | Artículos de revistas | |
