Microcode Compression Using Structured-Constrained Clustering

dc.creatorBorin, E
dc.creatorAraujo, G
dc.creatorBreternitz, M
dc.creatorWu, YF
dc.date2014
dc.dateFEB
dc.date2014-07-30T14:01:42Z
dc.date2015-11-26T16:17:09Z
dc.date2014-07-30T14:01:42Z
dc.date2015-11-26T16:17:09Z
dc.date.accessioned2018-03-28T23:01:52Z
dc.date.available2018-03-28T23:01:52Z
dc.identifierInternational Journal Of Parallel Programming. Springer/plenum Publishers, v. 42, n. 1, n. 140, n. 164, 2014.
dc.identifier0885-7458
dc.identifier1573-7640
dc.identifierWOS:000329403900008
dc.identifier10.1007/s10766-012-0206-9
dc.identifierhttp://www.repositorio.unicamp.br/jspui/handle/REPOSIP/56701
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/56701
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1267562
dc.descriptionModern microprocessors have used microcode as a way to implement legacy (rarely used) instructions, add new ISA features and enable patches to an existing design. As more features are added to processors (e.g. protection and virtualization), area and power costs associated with the microcode memory increased significantly. A recent Intel internal design targeted at low power and small footprint has estimated the costs of the microcode ROM to approach 20% of the total die area (and associated power consumption). Moreover, with the adoption of multicore architectures, the impact of microcode memory size on the chip area has become relevant, forcing industry to revisit the microcode size problem. A solution to address this problem is to store the microcode in a compressed form and decompress it at runtime. This paper describes techniques for microcode compression that achieve significant area and power savings, while proposes a streamlined architecture that enables high throughput within the constraints of a high performance CPU. The paper presents results for microcode compression on several commercial CPU designs which demonstrates compression ratios ranging from 50 to 62%. In addition, it proposes techniques that enable the reuse of (pre-validated) hardware building blocks that can considerably reduce the cost and design time of the microcode decompression engine in real-world designs.
dc.description42
dc.description1
dc.descriptionSI
dc.description140
dc.description164
dc.languageen
dc.publisherSpringer/plenum Publishers
dc.publisherNew York
dc.publisherEUA
dc.relationInternational Journal Of Parallel Programming
dc.relationInt. J. Parallel Program.
dc.rightsfechado
dc.rightshttp://www.springer.com/open+access/authors+rights?SGWID=0-176704-12-683201-0
dc.sourceWeb of Science
dc.subjectMicrocode compression
dc.subjectCode compression
dc.subjectMicroprocessor design
dc.subjectCompression algorithm
dc.subjectMicro-architecture
dc.subjectMicro-programming
dc.subjectCode Compression
dc.subjectArchitectures
dc.titleMicrocode Compression Using Structured-Constrained Clustering
dc.typeArtículos de revistas


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