Sparc16: A New Compression Approach For The Sparc Architecture

dc.creatorEcco L.
dc.creatorLopes B.
dc.creatorXavier E.C.
dc.creatorPannain R.
dc.creatorCentoducatte P.
dc.creatorAzevedo R.
dc.date2009
dc.date2015-06-26T13:38:22Z
dc.date2015-11-26T14:59:42Z
dc.date2015-06-26T13:38:22Z
dc.date2015-11-26T14:59:42Z
dc.date.accessioned2018-03-28T22:11:14Z
dc.date.available2018-03-28T22:11:14Z
dc.identifier9780769538570
dc.identifierProceedings - Symposium On Computer Architecture And High Performance Computing. , v. , n. , p. 169 - 176, 2009.
dc.identifier15506533
dc.identifier10.1109/SBAC-PAD.2009.22
dc.identifierhttp://www.scopus.com/inward/record.url?eid=2-s2.0-73849130290&partnerID=40&md5=15d567c8e7c0e38b4fec25450c163aa7
dc.identifierhttp://www.repositorio.unicamp.br/handle/REPOSIP/93034
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/93034
dc.identifier2-s2.0-73849130290
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1256100
dc.descriptionRISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. Alternative encodings for instruction sets, such as MIPS16 and Thumb, represent an effective approach to deal with this drawback. This article proposes to apply a new encoding to the SPARCv8 architecture. Through extensive analysis of a program mix from the Mibench and Mediabench benchmark suites, we suggest a new 16-bit instruction set, easily translated to its 32-bit counterpart during execution time. Using the aforementioned program mix to infer how code could be represented in the proposed 16-bit ISA, compression ratios as low as 56% can be obtained. We also evaluated the cache behavior and showed reductions of 42% on cache misses that can increase performance up to 28% (for patricia program with 2KB cache). © 2009 IEEE.
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dc.languageen
dc.publisher
dc.relationProceedings - Symposium on Computer Architecture and High Performance Computing
dc.rightsfechado
dc.sourceScopus
dc.titleSparc16: A New Compression Approach For The Sparc Architecture
dc.typeActas de congresos


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