| dc.creator | Sousa E.R. | |
| dc.creator | Meloni L. | |
| dc.date | 2011 | |
| dc.date | 2015-06-30T20:32:02Z | |
| dc.date | 2015-11-26T14:50:53Z | |
| dc.date | 2015-06-30T20:32:02Z | |
| dc.date | 2015-11-26T14:50:53Z | |
| dc.date.accessioned | 2018-03-28T22:02:15Z | |
| dc.date.available | 2018-03-28T22:02:15Z | |
| dc.identifier | 9780769545387 | |
| dc.identifier | Proc.- 2011 Ieee International Conference On Hpcc 2011 - 2011 Ieee International Workshop On Ftdcs 2011 -workshops Of The 2011 Int. Conf. On Uic 2011- Workshops Of The 2011 Int. Conf. Atc 2011. , v. , n. , p. 493 - 499, 2011. | |
| dc.identifier | | |
| dc.identifier | 10.1109/HPCC.2011.70 | |
| dc.identifier | http://www.scopus.com/inward/record.url?eid=2-s2.0-81555198058&partnerID=40&md5=88982a4746a43e9efd6f9212beea33e7 | |
| dc.identifier | http://www.repositorio.unicamp.br/handle/REPOSIP/108272 | |
| dc.identifier | http://repositorio.unicamp.br/jspui/handle/REPOSIP/108272 | |
| dc.identifier | 2-s2.0-81555198058 | |
| dc.identifier.uri | http://repositorioslatinoamericanos.uchile.cl/handle/2250/1254297 | |
| dc.description | Recently, DSP and FPGA devices have been employed in cooperative computing architectures for embedded systems which has required high complexity computing process which in turn demanded efficient techniques capable of measuring the total effective gain of the partitioning of a given code. In order to meet that need and based on Amdahl's Law a mathematical model of analysis which takes into account various factors pertaining the decentralized processing between DSP and FPGA such as the involved communication mechanisms, processing capacity, complexity of algorithms, processor idle time, was proposed. A test scenario for the application of the proposed mathematical model which enables to assess the performance gain between the distributed and centralized processing models was also developed. based on the motion estimation algorithm commonly used in many compression standards of digital images such as the H.264/AVC. © 2011 IEEE. | |
| dc.description | | |
| dc.description | | |
| dc.description | 493 | |
| dc.description | 499 | |
| dc.description | IEEE,IEEE Computer Society,IEEE Technical Committee on Scalable Computing (TCSC) | |
| dc.description | Brogioli, M., Hardware/Software Co-design Methodology and DSP/FPGA Partitioning: A Case Study for Meeting Real-Time Processing Deadlines in 3.50 Mobile Receivers 49th IEEE International Midwest Symposium on Circuits and Systems, San Juan, Puerto Rico, 2006 | |
| dc.description | Sousa, E.R., Meloni, L.G.P., High-Performance Computing Based on Heterogeneous Architectures IEEE International Conference on Information Systems and Computational Intelligence - ICISCI 2011. Harbin, China, Janeiro de 2011, , ISBN: 978-1-4244-9646-4 | |
| dc.description | (2007) Cycle Counting and Profiling, , http://www.analog.com/static/imported-files/application_notes/EE-332%20. pdf, July | |
| dc.description | Agostini, L.V., (2002) "Project of Integrated Architectures for JPEG Image Compression" (in Portuguese), , Master Thesis, Federal University of Rio Grande do Sul, March | |
| dc.description | H.264/AVC Reference Software Encoder, , http://iphome.hhi.de/suehring/tml/, Fraunhofer Institute. disponível em: acessado em 08 de abril de 2011 | |
| dc.description | Amdahl, G.M., Validity of the single pro cessor approach to achieving large scale computing capabilities AFIPS Spring Joint Computer Conference,1967 | |
| dc.description | Gustafson, J.L., Reevaluating Amdahl's Law (1988) Communication ACM, pp. 532-533 | |
| dc.description | Rinnerthaler, F.F., Boosting the Performance of Embedded Vision Systems Using a DSP/FPGA Co-processor System (2007) IEEE International Conference on Systems, Man and Cybernetics, pp. 1142-1146 | |
| dc.description | Tung, D., Yang, G., (2009) H.264/AVC Video Encoder Realization and Acceleration on TI DM642 DSP | |
| dc.description | Meyer- Baese, U., (2003) Digital Signal Processing with Field Programmable Gate Arrays, , Second Edition, Springer, October | |
| dc.description | Parnell, K., Bryner, R., (2004) Comparing and Contrasting FPGA and Microprocess System Design and Development, , Xilinx Inc., July | |
| dc.description | (2011) Absolute-Difference Motion Estimation for Intel Pentium 4 Processors, , http://software.intel.com/en-us/articles/absolute-difference-motion- estimation-for-intel-pentiumr-4-processors/, available abril | |
| dc.language | en | |
| dc.publisher | | |
| dc.relation | Proc.- 2011 IEEE International Conference on HPCC 2011 - 2011 IEEE International Workshop on FTDCS 2011 -Workshops of the 2011 Int. Conf. on UIC 2011- Workshops of the 2011 Int. Conf. ATC 2011 | |
| dc.rights | fechado | |
| dc.source | Scopus | |
| dc.title | An Analytical Model Proposed For Evaluating Efficiency Of Partitioning Code In Hybrid Architectures Based On Dsp And Fpga | |
| dc.type | Actas de congresos | |
