Compiler Support For Selective Page Migration In Numa Architectures

dc.creatorPiccoli G.
dc.creatorSantos H.N.
dc.creatorRodrigues R.E.
dc.creatorPousa C.
dc.creatorBorin E.
dc.creatorQuintao Pereira F.M.
dc.date2014
dc.date2015-06-25T17:56:47Z
dc.date2015-11-26T14:46:19Z
dc.date2015-06-25T17:56:47Z
dc.date2015-11-26T14:46:19Z
dc.date.accessioned2018-03-28T21:55:58Z
dc.date.available2018-03-28T21:55:58Z
dc.identifier9781450328098
dc.identifierParallel Architectures And Compilation Techniques - Conference Proceedings, Pact. Institute Of Electrical And Electronics Engineers Inc., v. , n. , p. 369 - 380, 2014.
dc.identifier1089795X
dc.identifier10.1145/2628071.2628077
dc.identifierhttp://www.scopus.com/inward/record.url?eid=2-s2.0-84907065294&partnerID=40&md5=9f83e9837ff673804f3024648fe23416
dc.identifierhttp://www.repositorio.unicamp.br/handle/REPOSIP/87117
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/87117
dc.identifier2-s2.0-84907065294
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1252794
dc.descriptionCurrent high-performance multicore processors provide users with a non-uniform memory access model (NUMA). These systems perform better when threads access data on memory banks next to the core where they run. However, ensuring data locality is difficult. In this paper, we propose compiler analyses and code generation methods to support a lightweight runtime system that dynamically migrates memory pages to improve data locality. Our technique combines static and dynamic analyses and is capable of identifying the most promising pages to migrate. Statically, we infer the size of arrays, plus the amount of reuse of each memory access instruction in a program. These estimates rely on a simple, yet accurate, trip count predictor of our own design. This knowledge lets us build templates of dynamic checks, to be filled with values known only at runtime. These checks determine when it is profitable to migrate data closer to the processors where this data is used. Our static analyses are quadratic on the number of variables in a program, and the dynamic checks are O(1) in practice. Our technique does not require any form of user intervention, neither the support of a third-party middleware, nor modifications in the operating system's kernel. We have applied our technique on several parallel algorithms, which are completely oblivious to the asymmetric memory topology, and have observed speedups of up to 4x, compared to static heuristics. We compare our approach against Minas, a middleware that supports NUMA-aware data allocation, and show that we can outperform it by up to 50% in some cases. © 2014 ACM.
dc.description
dc.description
dc.description369
dc.description380
dc.descriptionACM SIGARCH,IEEE Computer Society,IFIP
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dc.languageen
dc.publisherInstitute of Electrical and Electronics Engineers Inc.
dc.relationParallel Architectures and Compilation Techniques - Conference Proceedings, PACT
dc.rightsfechado
dc.sourceScopus
dc.titleCompiler Support For Selective Page Migration In Numa Architectures
dc.typeActas de congresos


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