Cmos Temperature-stable Linearised Differential Pair

dc.creatorDias J.A.S.
dc.creatorde Moraes W.B.
dc.date1992
dc.date2015-06-30T14:22:05Z
dc.date2015-11-26T14:43:18Z
dc.date2015-06-30T14:22:05Z
dc.date2015-11-26T14:43:18Z
dc.date.accessioned2018-03-28T21:51:21Z
dc.date.available2018-03-28T21:51:21Z
dc.identifier
dc.identifierElectronics Letters. , v. 28, n. 25, p. 2350 - 2351, 1992.
dc.identifier135194
dc.identifier
dc.identifierhttp://www.scopus.com/inward/record.url?eid=2-s2.0-0027111012&partnerID=40&md5=9e3183d6e27eef0141b7b03e824808d8
dc.identifierhttp://www.repositorio.unicamp.br/handle/REPOSIP/99571
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/99571
dc.identifier2-s2.0-0027111012
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1251623
dc.descriptionA simple technique which employs a bias current with a positive nonlinear temperature coefficient is used to compensate for the temperature variations of the transconductance in a CMOS linearised differential pair. Simulated results show that a temperature drift of less than 100 ppm/°C can be obtained in the 0-100°C range.
dc.description28
dc.description25
dc.description2350
dc.description2351
dc.languageen
dc.publisher
dc.relationElectronics Letters
dc.rightsfechado
dc.sourceScopus
dc.titleCmos Temperature-stable Linearised Differential Pair
dc.typeArtículos de revistas


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