A Software Transactional Memory System For An Asymmetric Processor Architecture

dc.creatorGoldstein F.
dc.creatorBaldassin A.
dc.creatorCentoducatte P.
dc.creatorAzevedo R.
dc.creatorGarcia L.A.G.
dc.date2008
dc.date2015-06-30T19:14:33Z
dc.date2015-11-26T14:40:09Z
dc.date2015-06-30T19:14:33Z
dc.date2015-11-26T14:40:09Z
dc.date.accessioned2018-03-28T21:46:17Z
dc.date.available2018-03-28T21:46:17Z
dc.identifier
dc.identifierProceedings - Symposium On Computer Architecture And High Performance Computing. , v. , n. , p. 175 - 182, 2008.
dc.identifier15506533
dc.identifier10.1109/SBAC-PAD.2008.21
dc.identifierhttp://www.scopus.com/inward/record.url?eid=2-s2.0-58049180588&partnerID=40&md5=20d2304060713b2374496d5f4ef0146e
dc.identifierhttp://www.repositorio.unicamp.br/handle/REPOSIP/105392
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/105392
dc.identifier2-s2.0-58049180588
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1250299
dc.descriptionDue to the advent of multi-core processors and the consequent need for better concurrent programming abstractions, new synchronization paradigms have emerged. A promising one, known as software transactional memory (STM), aims to use transactions as the key synchronization mechanism to ease program development as well as increase its performance. Many (if not all) of the current STM implementations target homogeneous architectures. In this paper we describe an implementation of an STM system for an asymmetric architecture, the Cell BE. We evaluated our Transactional Software Cache (TSC) mechanism using a well-known micro-benchmark (IntSet) and the Genome application from STAMP. The results show that an STM implementation for the Cell architecture is feasible if the shared-memory programming model is adopted. When compared to a conventional lock-based implementation, the STM version of Genome obtained a performance gain of 84% and 24% with large and small input sets, respectively. © 2008 IEEE.
dc.description
dc.description
dc.description175
dc.description182
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dc.languageen
dc.publisher
dc.relationProceedings - Symposium on Computer Architecture and High Performance Computing
dc.rightsfechado
dc.sourceScopus
dc.titleA Software Transactional Memory System For An Asymmetric Processor Architecture
dc.typeActas de congresos


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