dc.creatorOttoni G.
dc.creatorAraujo G.
dc.date2003
dc.date2015-06-30T17:33:24Z
dc.date2015-11-26T14:12:54Z
dc.date2015-06-30T17:33:24Z
dc.date2015-11-26T14:12:54Z
dc.date.accessioned2018-03-28T21:13:36Z
dc.date.available2018-03-28T21:13:36Z
dc.identifier
dc.identifierMicroelectronics Journal. , v. 34, n. 11, p. 1009 - 1018, 2003.
dc.identifier262692
dc.identifier10.1016/S0026-2692(03)00169-1
dc.identifierhttp://www.scopus.com/inward/record.url?eid=2-s2.0-0142185114&partnerID=40&md5=e594c184a75c5543aad275a65e997471
dc.identifierhttp://www.repositorio.unicamp.br/handle/REPOSIP/102644
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/102644
dc.identifier2-s2.0-0142185114
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1242135
dc.descriptionEfficient address register allocation has been shown to be a central problem in code generation for processors with restricted addressing modes. This paper extends previous work on Global Array Reference Allocation (GARA), the problem of allocating address registers to array references in loops. It describes two heuristics to the problem, presenting experimental data to support them. In addition, it proposes an approach to solve GARA optimally which, albeit computationally exponential, is useful to measure the efficiency of other methods. Experimental results, using the MediaBench benchmark and profiling information, reveal that the proposed heuristics can solve the majority of the benchmark loops near optimality in polynomial-time. A substantial execution time speedup is reported for the benchmark programs, after compiled with the original and the optimized versions of GCC. © 2003 Published by Elsevier Ltd.
dc.description34
dc.description11
dc.description1009
dc.description1018
dc.descriptionThe GNU Compiler Collection Project, , http://gcc.gnu.org
dc.descriptionAho, A., Johnson, S., Optimal code generation for expression trees (1976) Journal of the ACM, 23 (3), pp. 488-501
dc.descriptionAho, A., Sethi, R., Ullman, J., (1986) Compilers, Principles, Techniques and Tools, , Boston: Addison-Wesley
dc.descriptionAraujo, G., Sudarsanam, A., Instruction, M.S., Instruction set design and optimizations for address computation in DSP processors (1996) Ninth International Symposium on Systems Synthesis, pp. 31-37. , IEEE
dc.descriptionBartley, D.H., Optimizing stack frame accesses for processors with restricted addressing modes (1992) Software Practice and Experience, 22 (2), p. 101
dc.descriptionBodik, R., Gupta, R., Array data-flow analysis for load-store optimizations in superscalar architectures (1996) International Journal of Parallel Programming, 24 (6), pp. 481-512
dc.descriptionBradlee, D., Eggers, S., Henry, R., Integrating register allocation and instruction scheduling for RISCs (1991) Proceedings of the Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 122-131. , April
dc.descriptionBriggs, P., Cooper, K., Kennedy, K., Torczon, L., Coloring heuristics for register allocation (1989) Proceedings of the ACM SIGPLAN'89 on Conference on Programming Language Design and Implementation, pp. 275-284. , July
dc.descriptionCallahan, D., Carr, S., Kennedy, K., Improving register allocation for subscripted variables (1990) ACM SIGPLAN Conference on Programming Languages Design and Implementation, pp. 53-65. , June
dc.descriptionCallahan, D., Koblenz, B., Register allocation via hierarchical graph coloring (1991) Proceedings of the ACM SIGPLAN'91 Conference on Programming Languages Design and Implementation, pp. 192-203. , June
dc.descriptionChaitin, G., Register allocation and spilling via graph coloring (1982) Proceedings of the ACM SIGPLAN'82 Symposium on Compiler Construction, pp. 98-105. , June
dc.descriptionChow, F., Hennessy, J.L., The priority-based coloring approach to register allocation (1990) ACM Transactions on Programming Language and Systems, 12 (4), pp. 501-536
dc.descriptionCintra, M., Araujo, G., Array reference allocation using SSA-Form and live range growth (2000) Proceedings of the ACM SIGPLAN LCTES 2000, pp. 26-33. , June
dc.descriptionCytron, R., Ferrante, J., Rosen, B., Wegman, M., Zadeck, F., An efficient method of computing static single assignment form (1989) Proceedings of the ACM POPL'89, pp. 23-25
dc.descriptionEckstein, E., Krall, A., Minimizing cost of local variables access for DSP-processors (1999) Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pp. 20-27. , May
dc.descriptionGebotys, C., DSP address optimization using a minimum cost circulation technique (1997) Proceedings of the International Conference on Computer-Aided Design, pp. 100-103. , November
dc.descriptionIEEE
dc.descriptionGoodman, J., Hsu, A., Code scheduling and register allocation in large basic blocks (1988) Proceedings of the Conference on Supercomputing, pp. 442-452. , July
dc.descriptionGupta, R., Soffa, M., Ombres, D., Efficient register allocation via coloring using clique separators (1994) ACM Transactions on Programming Language and Systems, 16 (3), pp. 370-386
dc.descriptionHitchcock C.Y. III, (1986) Addressing Modes for Fast and Optimal Code Generation, , PhD Thesis, Carnegie-Mellon University, Pittsburgh, PA, Dec
dc.descriptionLee, C., Potkonjak, M., Mangione-Smith, W.H., (1997) Mediabench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems
dc.descriptionLeupers, R., Basu, A., Marwedel, P., Optimized array index computation in DSP programs (1998) Proceedings of the ASP-DAC, , IEEE
dc.descriptionLeupers, R., David, F., A uniform optimization technique for offset assignment problems (1998) Proceedings of the ACM SIGDA 11th International Symposium on System Synthesis, pp. 3-8. , December
dc.descriptionLeupers, R., Marwedel, P., (2001) Retargetable Compiler Technology for Embedded Systems, , Dordrecht: Kluwer
dc.descriptionLiao, S., Devadas, S., Keutzer, K., Tjiang, S., Wang, A., Storage assignment to decrease code size (1995) Proceedings of 1995 ACM Conference on Programming Language Design and Implementation
dc.description(1998) Digital Signal Processor, , DSP1611/17/18/27/28/29
dc.descriptionMuchnick, S.S., (1997) Advanced Compiler Design and Implementation, , Los Altos, CA: Morgan Kaufmann
dc.descriptionOttoni, G., Rigo, S., Araujo, G., Rajagopalan, S., Malik, S., Optimal live range merge for address register allocation in embedded programs (2001) LNCS, 2027, pp. 274-288. , Proceedings of the 10th International Conference on Compiler Construction, CC2001
dc.descriptionBerlin: Springer
dc.descriptionRao, A., Pande, S., Storage assignment optimizations to generate compact and efficient code on embedded DSPs (1999) Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 128-138. , May
dc.descriptionSethi, R., Complete register allocation problems (1975) SIAM Journal of Computing, 4 (3), pp. 226-248
dc.descriptionSethi, R., Ullman, J., The generation of optimal code for arithmetic expressions (1970) Journal of the ACM, 17 (4), pp. 715-728
dc.descriptionWolfe, M.J., (1996) High Performance Compilers for Parallel Computing, , Boston: Addison-Wesley
dc.languageen
dc.publisher
dc.relationMicroelectronics Journal
dc.rightsfechado
dc.sourceScopus
dc.titleAddress Register Allocation For Arrays In Loops Of Embedded Programs
dc.typeArtículos de revistas


Este ítem pertenece a la siguiente institución