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Energy-performance tradeoffs in software transactional memory
(2012-12-01)
Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of ...
Energy-performance tradeoffs in software transactional memory
(2012-12-01)
Transactional memory (TM) is a new synchronization mechanism devised to simplify parallel programming, thereby helping programmers to unleash the power of current multicore processors. Although software implementations of ...
Adaptive resource allocation with job runtime uncertainty
(2017-10)
In this paper, we address the problem of dynamic resource allocation in presence of job run- time uncertainty. We develop an execution delay model for runtime prediction, and design an adaptive
stochastic allocation ...
Performance-energy trade-offs prediction and runtime selection for parallel applications on heterogeneous multiprocessing systems
(Universidade Federal do Rio Grande do NorteBrasilUFRNPROGRAMA DE PÓS-GRADUAÇÃO EM ENGENHARIA ELÉTRICA E DE COMPUTAÇÃO, 2021-07-15)
In the multi-core era, the size of the software operation space, i.e. hardware
configurations (number of cores and operating frequency) that provide different software performance and energy consumption, is significantly ...
A monitoring infrastructure for the quality assessment of cloud services
(Springer Nature, 2016)
Service Level Agreements (SLAs) specify the strict terms under which
cloud services must be provided. The assessment of the quality of services being
provided is critical for both clients and service providers. In this ...
Improving Speculative taskloop in Hardware Transactional Memory
(2021-01-01)
Previous work proposed and evaluated Speculative taskloop (STL) on Intel Core implementing new clauses and constructs in OpenMP. The results indicated that, despite achieving some speed-ups, there was a phenomenon called ...
A transactional runtime system for the Cell/BE architecture
(Academic Press Inc. Elsevier B.V., 2012-12-01)
Single-core architectures have hit the end of the road and industry and academia are currently exploiting new multicore design alternatives. In special, heterogeneous multicore architectures have attracted a lot of attention ...
A transactional runtime system for the Cell/BE architecture
(Academic Press Inc. Elsevier B.V., 2012-12-01)
Single-core architectures have hit the end of the road and industry and academia are currently exploiting new multicore design alternatives. In special, heterogeneous multicore architectures have attracted a lot of attention ...
LUTS: A lightweight user-level transaction scheduler
(2011-11-09)
Software Transactional Memory (STM) systems have poor performance under high contention scenarios. Since many transactions compete for the same data, most of them are aborted, wasting processor runtime. Contention management ...