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Plataforma para medição de forças na região plantar de pacientes normais e hemiplégicos
(2013-03-26)
This work describes an electronic system implementation with two force plates, 24 load cells with strain gages, signal conditioning circuit, interfacing circuit and data acquisition system, designed for measuring plantar ...
Plataforma para medição de forças na região plantar de pacientes normais e hemiplégicos
(2013-03-26)
This work describes an electronic system implementation with two force plates, 24 load cells with strain gages, signal conditioning circuit, interfacing circuit and data acquisition system, designed for measuring plantar ...
CMOS level shifters from 0 to 18 V output
(Springer, 2021)
A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 lm CMOS-HV technology, is presented. This family of circuits ...
A fully integrated physical activity sensing circuit for implantable pacemakers
(IEEE, 2004)
This paper shows the implementation of a fully integrated Gm-C 0.5-7Hz bandpass filter-amplifier with gain G=400, for a piezoelectric accelerometer which is part of a rate adaptive pacemaker. The fabricated circuit operates ...
The RISC-V in implantable medical devices
(RISC-V, 2019-12)
In this work, first, the case of implantable medical devices (IMDs) will be presented including state of the art and industry overview. The main characteristics of IMD ASICs are
discussed (technical, engineering, business ...
Capacitive driven-right-leg circuit design
(Inderscience Enterprises Ltd., 2015)
CMOS level shifters from 0 to 18 V output
(Springer, 2021)
A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 lm CMOS-HV technology, is presented. This family of circuits ...
CMOS level shifters from 0 to 18 V output
(Springer, 2021)
A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 lm CMOS-HV technology, is presented. This family of circuits ...