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Analysis and detection of wear-out failures in nanometer technologies
(Instituto Nacional de Astrofísica, Óptica y Electrónica, 2009)
A methodology for automated design and implementation of complex analog and digital CMOS integrated circuits applying a genetic algorithm and a CAD tool for multiobjective optimization.
(Instituto Tecnológico de Costa Rica, 2014)
This dissertation proposes an automated methodology to design and optimize electronic integrated circuits, something that could be called simulation-driven optimization. The concept of Pareto optimality or the so called ...
Desenvolvimento e comparação de circuitos integrados que constituem uma malha de captura de fase
(Universidade Tecnológica Federal do ParanáCampo MouraoBrasilEngenharia EletrônicaUTFPR, 2016-11-21)
The focus of this project was to study and develop several integrated circuits that compose a PLL, utilizing a linearized model, with equations relevant to the study of a closed loop system. The integrated circuits were ...
Teste de SRAMs baseado na integração de March teste e sensores de corrente on-chip
(Pontifícia Universidade Católica do Rio Grande do SulPorto Alegre, 2010)
Currently it’s possible to observe that the area devoted to memory elements in embedded systems (Systems-on-Chip, SoC) occupies the largest portion of the integrated circuits and due to the advance in Very Deep Sub-Micron ...
Teste de SRAMs baseado na integração de March teste e sensores de corrente on-chip
(Pontifícia Universidade Católica do Rio Grande do SulPorto Alegre, 2010)
Currently it’s possible to observe that the area devoted to memory elements in embedded systems (Systems-on-Chip, SoC) occupies the largest portion of the integrated circuits and due to the advance in Very Deep Sub-Micron ...