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A 110 nA pacemaker sensing channel in CMOS on silicon-on-insulator
(IEEE, 2002)
The design of a sensing channel for implantable cardiac pacemakers in CMOS on silicon-on-insulator (SOI) technology is presented. The total current consumption is lowered to only 110nA thanks to the optimization at the ...
A Gm-C bump equalizer for low-voltage low-power applications
(2004-09-07)
A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current ...
Test Modules Design for a SerDes Chip in 130 nm CMOS technology
(ITESO, 2016-07)
Optimal design of a classical CMOS OTA-Miller using numerical methods and SPICE simulations
(XIII International Workshop Iberchip, 2007-03)
Design of the Analog Transmitter Module in 130 nm CMOS technology
(ITESO, 2016-07)
Test Modules Design for a SerDes Chip in 130 nm CMOS technology
(ITESO, 2016-07)
Design of the Analog Transmitter Module in 130 nm CMOS technology
(ITESO, 2016-07)
Optimal design of a classical CMOS OTA-Miller using numerical methods and SPICE simulations
(XIII International Workshop Iberchip, 2007-03)