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An energy-efficient hierarchical architecture for time-interleaved SAR ADC
(Institute of Electrical and Electronics Engineers, 2019-06)
An energy-efficient sampling architecture for time interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The architecture avoids the use of sampling buffers in order to ...
A 6-bit 2GS/s CMOS Time-Interleaved ADC for Analysis of Mixed-Signal Calibration Techniques
(2014)
A 6-bit 2-GS/s time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 μm CMOS process. The architecture uses 8 time-interleaved track-and-hold ...
Digital analog converter for the extraction of test signals from mixed integrated circuits
(Springer International Publishing, 2021)
A 2GS/s 6-bit CMOS time-interleaved ADC for analysis of mixed-signal calibration techniques
(Springer, 2015-07)
A 2-GS/s 6-bit time interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) is designed and fabricated in a 0.13 lm CMOS process. The architecture uses 8 time-interleaved track-andhold ...
A simple encoding method for Sigma-Delta ADC based biopotential acquisition systems
(Taylor & Francis, 2017-10)
Sigma Delta analogue-to-digital converters allow acquiring the full dynamic range of biomedical signals at the electrodes, resulting in less complex hardware and increased measurement robustness. However, the increased ...
Projeto de um conversor analógico/digital por aproximações sucessivas de 12 bits
(Universidade Federal de Minas GeraisUFMG, 2011-12-07)
This work presents the project of a 12-bit successive approximation analog-to-digital converter (SAR ADC). The mixed-signal development stages use a specific methodology that starts with the design of high abstraction level ...
Sistema integrado de baixo consumo para aquisição de ECG e cálculo da VFC
(Universidade Federal de Santa MariaBrasilCiência da ComputaçãoUFSMPrograma de Pós-Graduação em Ciência da ComputaçãoCentro de Tecnologia, 2020-02-19)
This work proposes a low power consumption analog front-end to acquire ECG signals and
calculate heart rate variability (HRV), which has several biomedical applications. Many QRS
detectors use digital techniques (software) ...