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Amplificador de baixo ruído totalmente integrado em CMOS
(Universidade Federal de Pernambuco, 2014)
An analog implementation of radial basis neural networks (RBNN) using BiCMOS technology
(2001-12-01)
This paper describes a analog implementation of radial basis neural networks (RBNN) in BiCMOS technology. The RBNN uses a gaussian function obtained through the characteristic of the bipolar differential pair. The gaussian ...
An analog implementation of radial basis neural networks (RBNN) using BiCMOS technology
(2001-12-01)
This paper describes a analog implementation of radial basis neural networks (RBNN) in BiCMOS technology. The RBNN uses a gaussian function obtained through the characteristic of the bipolar differential pair. The gaussian ...
CMOS level shifters from 0 to 18 V output
(Springer, 2021)
A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 lm CMOS-HV technology, is presented. This family of circuits ...
¿Cómo vaciar la CMOS para resetear los ajustes de la BIOS?
(Cátedras - Facultad de Ingeniería y Tecnología Informática - Universidad de Belgrano, 2015-06-10)
¿Cómo vaciar la CMOS para resetear los ajustes de la BIOS?
Charge-Pump Circuit in 65nm CMOS for Neural Stimulation on Deep-Brain Stimulation
(2021-01-01)
Deep-Brain Stimulation (DBS) is an emerging area to improve the life of patients with brain deceases and one with the most dynamic research towards implantable devices. This paper presents an electronic circuit to generate ...
A methodology for automated design and implementation of complex analog and digital CMOS integrated circuits applying a genetic algorithm and a CAD tool for multiobjective optimization.
(Instituto Tecnológico de Costa Rica, 2014)
This dissertation proposes an automated methodology to design and optimize electronic integrated circuits, something that could be called simulation-driven optimization. The concept of Pareto optimality or the so called ...
A Gm-C bump equalizer for low-voltage low-power applications
(2004-09-07)
A low-voltage low-power 2nd-order CMOS pseudo-differential bump-equalizer is presented. Its topology comprises a bandpass section with adjustable center frequency and quality factor, together with a programmable current ...