| dc.contributor | VICTOR HUGO CHAMPAC VILELA | |
| dc.creator | JESUS MORENO MORENO | |
| dc.date | 2012-06 | |
| dc.date.accessioned | 2023-07-25T16:21:17Z | |
| dc.date.available | 2023-07-25T16:21:17Z | |
| dc.identifier | http://inaoe.repositorioinstitucional.mx/jspui/handle/1009/293 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7805513 | |
| dc.description | CMOS IC scaling has provided significant improvements in electronic circuit performance.
Advances in test methodologies to deal with new failure mechanisms and nanometer issues
are required. Interconnect opens are an important defect mechanism that requires detailed
knowledge of its physical properties. In nanometer process, variability is predominant and
considering only nominal value of parameters is not realistic. In this thesis, a model for
computing a realistic coverage of via open defects that takes into account the process
variability is proposed. Spatial and parametric correlation between device parameters,
spatial correlation between interconnect parameters, random dopant fluctuation and trapped
gate charge are considered. Furthermore, these factors can also influence the detection of
the defect. In addition, the detection capability of Low Voltage Testing for interconnect
opens, considering process variations, is evaluated using a statistical model. The proposed
methodology is implemented in a software tool to determine the probability of detection of
via opens for some ISCAS benchmark circuits. The proposed detection probability
evaluation together with a test methodology to generate favorable logic conditions at the
coupling lines can allow a better test quality leading to higher product reliability. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | Instituto Nacional de Astrofísica, Óptica y Electrónica | |
| dc.relation | citation:Moreno-Moreno J. | |
| dc.rights | info:eu-repo/semantics/openAccess | |
| dc.rights | http://creativecommons.org/licenses/by-nc-nd/4.0 | |
| dc.subject | info:eu-repo/classification/Circuitos/Circuit CAD | |
| dc.subject | info:eu-repo/classification/Pruebas estadísticas/Statistical testing | |
| dc.subject | info:eu-repo/classification/Sitios de prueba de áreas abiertas/Open area test sites | |
| dc.subject | info:eu-repo/classification/Confiabilidad/Reliability | |
| dc.subject | info:eu-repo/classification/cti/1 | |
| dc.subject | info:eu-repo/classification/cti/22 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.subject | info:eu-repo/classification/cti/2203 | |
| dc.title | Realistic detection of interconnect opens under process variations | |
| dc.type | info:eu-repo/semantics/doctoralThesis | |
| dc.type | info:eu-repo/semantics/acceptedVersion | |
| dc.audience | students | |
| dc.audience | researchers | |
| dc.audience | generalPublic | |
