Article
A Reorder Buffer Design for High Performance Processors
Fecha
2012-03-15Registro en:
Revista Computación y Sistemas; Vol. 16 No. 1
1405-5546
Autor
García Ordaz, José R.
Ramírez Salinas, Marco A.
Villa Vargas, Luis A.
Molina Lozano, Herón
Peredo Macías, Cuauhtémoc
Institución
Resumen
Abstract. Modern reorder buffers (ROBs) were
conceived to improve processor performance by
allowing instruction execution out of the original
program order and run ahead of sequential instruction
code exploiting existing instruction level parallelism
(ILP). The ROB is a functional structure of a processor
execution engine that supports speculative execution,
physical register recycling, and precise exception
recovering. Traditionally, the ROB is considered as a
monolithic circular buffer with incoming instructions at
the tail pointer after the decoding stage and
completing instructions at the head pointer after the
commitment stage. The latter stage verifies instructions
that have been dispatched, issued, executed, and are
not completed speculatively. This paper presents a
design of distributed reorder buffer microarchitecture
by using small structures near building blocks which
work together, using the same tail and head pointer
values on all structures for synchronization. The
reduction of area, and therefore, the reduction of
power and delay make this design suitable for both
embedded and high performance microprocessors.