A retargetable VLIW compiler framework for DSPs with instruction-level parallelism

dc.creatorRajagopalan, S
dc.creatorRajan, SP
dc.creatorMalik, S
dc.creatorRigo, S
dc.creatorAraujo, G
dc.creatorTakayama, K
dc.date2001
dc.dateNOV
dc.date2014-11-17T03:58:12Z
dc.date2015-11-26T16:37:42Z
dc.date2014-11-17T03:58:12Z
dc.date2015-11-26T16:37:42Z
dc.date.accessioned2018-03-28T23:20:52Z
dc.date.available2018-03-28T23:20:52Z
dc.identifierIeee Transactions On Computer-aided Design Of Integrated Circuits And Systems. Ieee-inst Electrical Electronics Engineers Inc, v. 20, n. 11, n. 1319, n. 1328, 2001.
dc.identifier0278-0070
dc.identifierWOS:000171786000006
dc.identifier10.1109/43.959861
dc.identifierhttp://www.repositorio.unicamp.br/jspui/handle/REPOSIP/53695
dc.identifierhttp://www.repositorio.unicamp.br/handle/REPOSIP/53695
dc.identifierhttp://repositorio.unicamp.br/jspui/handle/REPOSIP/53695
dc.identifier.urihttp://repositorioslatinoamericanos.uchile.cl/handle/2250/1272095
dc.descriptionA standard design methodology for embedded processors today is the system-on-a-chip design with potentially multiple heterogeneous processing elements on a chip, such as a very long instruction word (VLIW) processor, digital signal processor (DSP), and field-programmable gate array. To be able to program these devices, we need compilers that are capable of generating efficient code for the different types of processing elements with efficiency measured in terms of power, area, and execution time. In addition, the compilers should also be highly retargetable to enable the system designer to quickly evaluate different cores for the application on hand and reduce the time to market. In this paper, we show that we can extend a conventional VLIW compilation environment to develop highly retargetable optimizing compilers for DSPs with irregular architectures. We have used the second generation Fujitsu Hiperion fixed-point DSP as our primary example to evaluate the compiler framework. We demonstrate through experimental results that execution time for the assembly code generated using our framework is roughly two times better than that of the code generated by a widely used commercially available DSP compiler. Even without incorporating DSP-specific optimizations in our extended VLIW framework, we demonstrate that the compiled code has a better performance than the code generated by a commercial DSP-specific compiler in all our examples.
dc.description20
dc.description11
dc.description1319
dc.description1328
dc.languageen
dc.publisherIeee-inst Electrical Electronics Engineers Inc
dc.publisherPiscataway
dc.publisherEUA
dc.relationIeee Transactions On Computer-aided Design Of Integrated Circuits And Systems
dc.relationIEEE Trans. Comput-Aided Des. Integr. Circuits Syst.
dc.rightsfechado
dc.rightshttp://www.ieee.org/publications_standards/publications/rights/rights_policies.html
dc.sourceWeb of Science
dc.subjectDSP compiler
dc.subjectirregular architecture
dc.subjectoptimization
dc.subjectsystem on a chip
dc.titleA retargetable VLIW compiler framework for DSPs with instruction-level parallelism
dc.typeArtículos de revistas


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