| dc.creator | Dos Santos C.R. | |
| dc.creator | Motoyama S. | |
| dc.date | 2005 | |
| dc.date | 2015-06-26T14:09:55Z | |
| dc.date | 2015-11-26T14:09:44Z | |
| dc.date | 2015-06-26T14:09:55Z | |
| dc.date | 2015-11-26T14:09:44Z | |
| dc.date.accessioned | 2018-03-28T21:10:17Z | |
| dc.date.available | 2018-03-28T21:10:17Z | |
| dc.identifier | | |
| dc.identifier | Proceedings - 2005 Systems Communications: Icw 2005, Wireless - Ichsn 2005, High Speed Networks - Icmcs 2005, Multimedia Communications Systems - Senet 2005, Sensor Networks. , v. 2005, n. , p. 241 - 247, 2005. | |
| dc.identifier | | |
| dc.identifier | 10.1109/ICW.2005.15 | |
| dc.identifier | http://www.scopus.com/inward/record.url?eid=2-s2.0-33646916344&partnerID=40&md5=c399d8b6f2cedbe3373812ae42092f9c | |
| dc.identifier | http://www.repositorio.unicamp.br/handle/REPOSIP/93912 | |
| dc.identifier | http://repositorio.unicamp.br/jspui/handle/REPOSIP/93912 | |
| dc.identifier | 2-s2.0-33646916344 | |
| dc.identifier.uri | http://repositorioslatinoamericanos.uchile.cl/handle/2250/1241310 | |
| dc.description | A QoS provisioned CIOQ switch using crossbar structure with m parallel lines per output port is proposed in this paper. The packets at input buffers are transferred to the output buffers by means of mxN internal lines. Since all internal lines have the same speed as external links, no internal clock speedup is required so that the proposed structure is suited for high-speed switches. The switch models for analysis are proposed and its performances are evaluated by means of queuing theory. The results show that only 2 internal links for each output port are sufficient for quick packet transfer from the input buffers to the output buffers. The proposed switch has also the feature that facilitates the choice of scheduler in order to satisfy the QoS of each class of service. © 2005 IEEE. | |
| dc.description | 2005 | |
| dc.description | | |
| dc.description | 241 | |
| dc.description | 247 | |
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| dc.description | Newman, P., Minshall, G., Lyon, T., Huston, L., IP switching and gigabit routers (1977) IEEE Comm. Magazine, pp. 64-69. , January | |
| dc.description | Motoyama, S., Arantes, M.P., An IP switch with distributed scheduling (2002) IEE Electronics Letters, 38 (8), pp. 392-393. , April | |
| dc.description | Minkenberg, C., Engbersen, T., A combined input and output queued packet-switched system based on PRIZMA switch-on-a-chip technology (2000) IEEE Commun. Magazine, 38 (12), pp. 70-77. , December | |
| dc.description | Chuang, S.T., Goel, A., Nckeown, N., Prabhakar, B., Matching output queuing with a combined input output queued switch (1999) IEEE Journal on Selected Areas in Communications, 17 (6), pp. 1030-1039. , June | |
| dc.description | Yang, M., Zheng, S.Q., An efficient scheduling algorithm for CIOQ switches with space-division multiplexing expansion Proc. IEEE Infocom'2003 | |
| dc.description | Motoyama, S., Santos, C.R., A combined input-output queuing ATM switch with m internal links for cell transfer (2002) International Telecommunications Symposium, pp. 142-146. , September | |
| dc.description | Motoyama, S., Santos, C.R., Performance analysis of a CIOQ ATM switch with m internal links for cell transfer (2002) 10th International Conference on Software, Telecommunications & | |
| dc.description | Computer Networks - SoftCom 2002, pp. 636-640. , November | |
| dc.description | Santos, C.R., Motoyama, S., A QoS provisioned CIOQ ATM switch with m internal links (2004) 11th International Conference on Telecommunications - ICT 2004, pp. 698-703. , Fortaleza, Brazil, August | |
| dc.language | en | |
| dc.publisher | | |
| dc.relation | Proceedings - 2005 Systems Communications: ICW 2005, Wireless - ICHSN 2005, High Speed Networks - ICMCS 2005, Multimedia Communications Systems - SENET 2005, Sensor Networks | |
| dc.rights | fechado | |
| dc.source | Scopus | |
| dc.title | A Qos Provisioned Cioq Packet Switch Using Crossbar Structure With M Internal Links | |
| dc.type | Actas de congresos | |
