Otro
Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process
Registro en:
Analog Integrated Circuits and Signal Processing. Dordrecht: Springer, v. 65, n. 1, p. 61-66, 2010.
0925-1030
10.1007/s10470-009-9412-9
WOS:000282012800006
Autor
Oliveira, Vlademir J. S.
Oki, Nobuo
Resumen
An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mu m AMS CMOS. process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz. Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)