This thesis presents a methodology to design a Fractional Frequency Synthesizer. The research lead to many problems that where not completely solved up to the publication time of this work. The main objective of the research was the reduction of spur tones in the total phase noise figure due to the periodicity in the digital §¢ modulator. The proposed solution for the spur tones reduction is an efficient way to add a dither signal in a MASH 1-1-1 architecture. The behavioral models are a good tool to model this mixed signal systems but it is difficult to include all the noise sources in the system. New simulation scripts are developed to improve the accuracy in the phase noise prediction. Also, the proposed behavioral models are more direct from the circuit designer’s point of view. New design considerations where developed for the voltage controlled oscillator to improve the linear tuning range. The programable frequency divider was designed to be unsensitive to the process, voltage and temperature variations. Finally a statistical model was developed for the phase to frequency detector which helps to design a delay in the gates building this digital circuit. All the design considerations can be used to improve the performance of this mixed signal circuit and even used for other applications to innovate the integrated circuit design to solve the people problems.