| dc.contributor | Aguilera-Galicia, Cuauhtemoc R. | |
| dc.creator | Moreno-Contreras, Mario A. | |
| dc.date | 2020-11-10T20:49:18Z | |
| dc.date | 2020-11-10T20:49:18Z | |
| dc.date | 2020-10 | |
| dc.date.accessioned | 2023-07-21T21:51:46Z | |
| dc.date.available | 2023-07-21T21:51:46Z | |
| dc.identifier | Moreno-Contreras, M. A. (2020). A predictive control unit for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle oriented to Audio Applications. Trabajo de obtención de grado, Especialidad en Diseño de Sistemas en Chip. Tlaquepaque, Jalisco: ITESO. | |
| dc.identifier | https://hdl.handle.net/11117/6391 | |
| dc.identifier.uri | https://repositorioslatinoamericanos.uchile.cl/handle/2250/7753639 | |
| dc.description | This document presents the implementation of a new predictive algorithm for a 10-bit analogto-digital converter based on the successive approximation register (SAR), technique. The predictive algorithm (PSAR), is designed to predict a specific number of consecutive bits depending on the difference between the analog input voltage (Vin) and the reference voltage (Vref), provided by the DAC used in the successive approximation conversion technique. The PSAR is able to predict from 3 bits to 8 bits in a single conversion cycle. The typical SAR conversion employs a comparison between Vin and Vref on the voltage domain. In the case of the proposed PSAR, the Vin and Vref are converted to a time pulse width proportional to the magnitude of the inputs and the comparison of both is made in the time domain. The time difference between these two pulses is compared and registered by a counter to determine the total number of consecutive bits to predict. The proposed PSAR requires 13 clock cycles to perform conversion if there are not more than 2 consecutive bits to predict. The PSAR reduce 21% of the average conversion time when an ascendant ramp with the 1024 possible input values is applied. | |
| dc.description | ITESO, A. C. | |
| dc.format | application/pdf | |
| dc.language | eng | |
| dc.publisher | ITESO | |
| dc.rights | http://quijote.biblio.iteso.mx/licencias/CC-BY-NC-ND-2.5-MX.pdf | |
| dc.subject | Analog to Digital Converter | |
| dc.subject | Predictive Algorithm | |
| dc.title | A predictive control unit for a Low Power 10-bit 200kS/s SAR ADC with Adaptive Conversion Cycle oriented to Audio Applications | |
| dc.type | info:eu-repo/semantics/academicSpecialization | |
| dc.type | info:eu-repo/semantics/submittedVersion | |
