article
Set-reset flip-flop circuit with a simple output logic
Registro en:
Campos-Cantón, I., Campos-Cantón, E., Rosu, H.C. et al. Circuits Syst Signal Process (2012) 31: 753.
Autor
Campos Cantón, Isaac
Campos Cantón, Eric
Rosu Barbus, Haret-Codratian
Castellanos Velasco, E.
Resumen
"The equation of the plane (EOP) in analytic geometry is used to build a logic dynamic architecture, i.e., a combination of set-reset flip-flop (SR-FF) and basic logic gates. This is achieved by using two of the variables in the EOP as the input signals of the SR-FF and the remaining variable as the output signal. This theoretical proposal for mixing the SR-FF and the basic logic gates is confirmed experimentally by means of a simple electronic implementation."