info:eu-repo/semantics/article
Direct Optimization of a PCI Express Link Equalization in Industrial Post-Silicon Validation
Fecha
2018-03Registro en:
F. E. Rangel-Patiño, J. E. Rayas-Sánchez, E. A. Vega-Ochoa and N. Hakim, "Direct optimization of a PCI express link equalization in industrial post-silicon validation," 2018 IEEE 19th Latin-American Test Symposium (LATS), Sao Paulo, 2018, pp. 1-6. doi: 10.1109/LATW.2018.8347238
2373-0862
Autor
Rangel-Patiño, Francisco E.
Rayas-Sánchez, José E.
Vega-Ochoa, Edgar A.
Hakim, Nagib