bachelorThesis
Ensaios de aceleração computacional de alguns algoritmos clássicos utilizando-se FPGA
Fecha
2021-08-17Registro en:
COLET, João Mateus. Ensaios de aceleração computacional de alguns algoritmos clássicos utilizando-se FPGA. 2021. Trabalho de Conclusão de Curso (Engenharia de Computação) - Universidade Tecnológica Federal do Paraná (UTFPR), Pato Branco, 2021.
Autor
Colet, João Mateus
Resumen
With the increasing complexity of computational algorithms, conventional technologies began to show unsatisfactory results regarding processing time. New technologies for code acceleration have emerged to address the disadvantages of sequential-code computers, including the FPGAs. Through the re-reading of an old concept, called F+V architecture, proposed by Estrin (1960), consisting of a sequential processor and an FPGA, it were combined the advantages of both technologies by exploring parallelism in the proposed problems. This work verified through scientific essays the acceleration achieved through this proposal of the classical problems: the detector of prime numbers, the bubble sort sorting algorithm and the Z buffer image rendering algorithm. Acceleration results were achieved in the order of up to 200 thousand, 9 and 1.3 times respectively. Showing the advantages of use FPGA in F+V architecture.