Diseño de un acelerador de hardware para simulaciones de redes neuronales biológicamente precisas utilizando un sistema multi-FPGA

Abstract

An FPGA-synthesizable IP was implemented in order to compute a neural network using the extended Hodgkin-Huxley algorithm. An Euler aproximation algorithm written in the programming language C was used as input code, subject to synthesize the IP using the Vivado HLS Synthesis tool from Xilinx. The IP can work in parallel among several devices, so the computation is also parallelized, increasing thus the computational performance. The ZedBoard development board was used to test the generated IP. The software needed to manage the simulation programming initialization and data movement was implemented using di erent approaches: one using a bare metal implementation, and another using an embedded operating system. The interfaces used in the IP were the AXI4-Lite and AXI4-Stream, and a comparation of data transfer speeds was carried on. Also, some comparisons of performance between the implementation of the IP with the operative system and standalone system were carried on. Finally, the computational precision of the system was tested, using the C program as a reference.