info:eu-repo/semantics/article
7 TOPS/W Cellular Neural Network Processor Core for Intelligent Internet-of-Things
Fecha
2019-08Registro en:
Villemur, Martin; Julian, Pedro Marcelo; Figliolia, Tomas; Andreou, Andreas; 7 TOPS/W Cellular Neural Network Processor Core for Intelligent Internet-of-Things; Institute of Electrical and Electronics Engineers; IEEE Transactions on Circuits and Systems II: Express Briefs; 8-2019; 1-5
1549-7747
1558-3791
CONICET Digital
CONICET
Autor
Villemur, Martin
Julian, Pedro Marcelo
Figliolia, Tomas
Andreou, Andreas
Resumen
We discuss the architecture, implementation and testing of a simplicial Cellular Neural Network (CNN) vector processor core aimed at vision oriented intelligent Internet-of-Things (IoT) devices. The architecture comprises a linear array of 64 processing elements (PE), each connected to a 4 neighbor clique operating on 8-bit input and state data. A 3-bit simplicial parameter, allows multilevel function approximation and extends the functionality over previously reported chips. Input data vectors are stored in two 64 x 64 x 8-bit data caches. The chip is synthesized from a custom designed ultra low voltage CMOS library and fabricated in a 55nm CMOS technology. Dynamic voltage/frequency scaling allows operation at power supplies between 0.5 and 1.2 Volts allowing for a tradeoff between speed and power. The fabricated chip achieves an overall performance of 7.05 TOPS/W at 732fps, with a dynamic energy efficiency of 12.2fJ per operation (OP) at 1.2 Volts.